Datasheet LTM4634 (Analog Devices) - 7

LTM4634
Typical perForMance characTerisTics 24V to 5V Full Load Short Start-Up into Pre-Bias Steady-State Output Ripple
RUN 5V/DIV V V OUT OUT RIPPLE 2V/DIV VOUT1 1V/DIV 10mV/DIV SW NODE IIN SW 5V/DIV 1A/DIV 10V/DIV 20µs/DIV 4634 G19 VIN = 24V 20ms/DIV 4634 G20 2µs/DIV 4634 G21 VOUT = 5V PREBIAS 1.5V OUTPUT STARTING AT 0.5V BIAS 12V TO 3.3V AT 5A LOAD IOUT = 5A 12V INPUT COUT = 2 × 100µF X5R 1210
pin FuncTions PACKAGE ROW AND COLUMN LABELING MAY VARY VIN1,VIN2,VIN3 (F9-F10,G9-G10,H9-H10);(F5-F6,G5- AMONG µModule PRODUCTS. REVIEW EACH PACKAGE G6,H5-H6);(F1-F2,G1-G2,H1-H2):
Power Input Pins.
LAYOUT CAREFULLY.
Apply input voltage between these pins and the GND pins.
GND (A4, A8-A9, D1- D12, E1-E12, F4, F8, F12, G3-G4,
Recommend placing input decoupling capacitance directly
G7-G8, G11-G12, H3-H4, H7-H8, H11-H12, J1-J5, J7,
between the VIN pins and the GND pins. The VIN paths
J9-J12, K1-K3, K8-K10, K12,L1-L2,L12, M1, M6-M8,
can be all combined from one power source, or powered
M12):
Ground Pins for Both Input and Output Returns. from independent power sources. See the Applications All ground pins need to connect with large copper areas Information section. underneath the unit.
SW1 (F11), SW2 (F7), SW3 (F3):
The internal switch
VOUT1, VOUT2, VOUT3 (A10-A12, B9-B12, and C10-C12);
node for each of the regulator channels for monitoring
(A5-A7, B5-B8, C6-C8); (A1-A3, B1-B4, C1-C4):
Power the switching waveform. An R-C snubber circuit can be Output Pins. Apply output load between these pins and placed on these pins to ground to eliminate switch node the GND pins. Recommend placing output decoupling ringing noise. capacitance directly between these pins and the GND
CNTL_PWR (J6):
Input Supply to an Internal Bias LDO to pins. See Table 4. Power the Internal Controller and MOSFET Drivers. The
TEMP1 AND TEMP2 (C9, C5):
Two Onboard Temperature operating voltage range is 4.75V to 28V under all condi- Diodes for Monitoring the VBE Junction Voltage Change tions. If the voltage at CNTL_PWR is ≤5.8V, the INTVCC with Temperature. Each of these two temperature diode pin should be tied to CNTL_PWR for optimum efficiency. connected PNP transistors is placed in the middle of If the voltage at CNTL_PWR is >5.8V, leave INTVCC float- channel 1 and channel 2, and in the middle of channel 2 ing with the recommended decoupling capacitor. To and channel 3. See the Applications Information section eliminate power loss in the onboard linear regulator and and an example in Figure 25. Leave floating if not used. improve efficiency connect a 5V supply at EXTVCC. Ensure CNTL_PWR > EXTVCC at all times to avoid reverse polarity on the internal bias LDO. 4634f For more information www.linear.com/LTM4634 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Related Parts