Datasheet PCF8574, PCF8574A (NXP) - 9

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NXP Semiconductors PCF8574; PCF8574A Remote 8-bit I/O expander for I2C-bus with interrupt 8.3 Reading from a port (Input mode)
The port must have been previously written to logic 1, which is the condition after power-on reset. To enter the Read mode the master (microcontroller) addresses the slave device and sets the last bit of the address byte to logic 1 (address byte read). The slave will acknowledge and then send the data byte to the master. The master will NACK and then send the STOP condition or ACK and read the input register again. The read of any pin being used as an output will indicate HIGH or LOW depending on the actual state of the pin. If the data on the input port changes faster than the master can read, this data may be lost. The DATA 2 and DATA3 are lost because these data did not meet the setup time and hold time (see Figure 9). no acknowledge from master slave address data from port data from port SDA S A6 A5 A4 A3 A2 A1 A0 1 A DATA 1 A DATA 4 1 P START condition R/W acknowledge acknowledge STOP from slave from master condition read from port DATA 2 data at DATA 1 DATA 3 DATA 4 port th(D) tsu(D) INT tv(INT) trst(INT) trst(INT) 002aah383 A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost.
Fig 9. Read mode (input)
Simple code for Read mode: <S> <slave address + read> <
ACK
> <
data in
> <ACK> ... <
data in
> <ACK> <
data in
> <NACK> <P>
Remark:
Bold type = generated by slave device.
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCF8574/74A in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCF8574/74A registers and I2C-bus/SMBus state machine will initialize to their default states of all I/Os to inputs with weak current source to VDD. Thereafter VDD must be lowered below VPOR and back up to the operation voltage for power-on reset cycle. PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 27 May 2013 9 of 33
Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 4.1 Ordering options 5. Block diagram 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description 7.1 Device address 7.1.1 Address maps 8. I/O programming 8.1 Quasi-bidirectional I/Os 8.2 Writing to the port (Output mode) 8.3 Reading from a port (Input mode) 8.4 Power-on reset 8.5 Interrupt output (INT) 9. Characteristics of the I2C-bus 9.1 Bit transfer 9.1.1 START and STOP conditions 9.2 System configuration 9.3 Acknowledge 10. Application design-in information 10.1 Bidirectional I/O expander applications 10.2 How to read and write to I/O expander (example) 10.3 High current-drive load applications 10.4 Migration path 11. Limiting values 12. Thermal characteristics 13. Static characteristics 14. Dynamic characteristics 15. Package outline 16. Handling information 17. Soldering of SMD packages 17.1 Introduction to soldering 17.2 Wave and reflow soldering 17.3 Wave soldering 17.4 Reflow soldering 18. Soldering of through-hole mount packages 18.1 Introduction to soldering through-hole mount packages 18.2 Soldering by dipping or by solder wave 18.3 Manual soldering 18.4 Package related soldering information 19. Soldering: PCB footprints 20. Abbreviations 21. Revision history 22. Legal information 22.1 Data sheet status 22.2 Definitions 22.3 Disclaimers 22.4 Trademarks 23. Contact information 24. Contents