Datasheet AT90S2323, AT90LS2323, AT90S2343, AT90LS2343 (Atmel) - 7

AT90S/LS2323/2343
Architectural
Overview The fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from
the register file, the operation is executed and the result is stored back in the register file
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing, enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the constant table look-up function. These added function registers are the 16-bit X-, Y-, and Z-register.
Figure 5. The AT90S2323/2343 AVR RISC Architecture Data Bus 8-bit 1K x 16
Program
Flash Program
Counter Status
and Test 32 x 8
General
Purpose
Registers Control Lines Direct Addressing Instruction
Decoder Indirect Addressing Instruction
Register Control
Registers
Interrupt
Unit
SPI
Unit
8-bit
Timer/Counter ALU
Watchdog
Timer 128 x 8
Data
SRAM I/O Lines 128 x 8
EEPROM The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 5
shows the AT90S2323/2343 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be
used on the register file as well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 -$1F), allowing them to be
accessed as though they were ordinary memory locations.
The I/O memory space contains 64 addresses for CPU peripheral functions such as
Control Registers, Timer/Counters, A/D converters and other I/O functions. The I/O
memory can be accessed directly or as the Data Space locations following those of the
register file, $20 -$5F. 7
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