Datasheet ATtiny15L (Atmel) - 9

link to page 36
ATtiny15L
Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 511), and LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB = 1).
Subroutine and Interrupt
The ATtiny15L uses a 3-level-deep Hardware Stack for subroutines and interrupts. The
Hardware Stack
Hardware Stack is nine bits wide and stores the Program Counter (PC) return address while subroutines and interrupts are executed. RCALL instructions and interrupts push the PC return address onto Stack level 0, and the data in the other Stack levels 1 - 2 are pushed one level deeper in the Stack. When a RET or RETI instruction is executed the returning PC is fetched from Stack level 0, and the data in the other Stack levels 1 - 2 are popped one level in the Stack. If more than three subsequent subroutine calls or interrupts are executed, the first val- ues written to the Stack are overwritten. Pushing four return addresses A1, A2, A3, and A4 followed by four subroutine or interrupt returns, will pop A4, A3, A2, and once more A2 from the Hardware Stack.
The EEPROM Data
The ATtiny15L contains 64 bytes of data EEPROM memory. It is organized as a sepa-
Memory
rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 36, specifying the EEPROM Address Register, the EEPROM Data Register, and the EEPROM Control Register.
Memory Access and
This section describes the general access timing concepts for instruction execution and
Instruction Execution Timing
internal memory access. The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 10 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 10.
The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 11 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.
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1187H–AVR–09/07 Document Outline Features Pin Configuration Description Block Diagram Pin Descriptions VCC GND Port B (PB5..PB0) Analog Pins Internal Oscillators ATtiny15L Architectural Overview The General Purpose Register File The ALU - Arithmetic Logic Unit The Flash Program Memory The Program and Data Addressing Modes Register Direct, Single- register Rd Register Indirect Register Direct, Two Registers Rd and Rr I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing using the LPM Instruction Subroutine and Interrupt Hardware Stack The EEPROM Data Memory Memory Access and Instruction Execution Timing I/O Memory The Status Register - SREG Reset and Interrupt Handling ATtiny15L Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Status Register - MCUSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Interrupt Handling Interrupt Response Time The General Interrupt Mask Register - GIMSK The General Interrupt Flag Register - GIFR The Timer/Counter Interrupt Mask Register - TIMSK The Timer/Counter Interrupt Flag Register - TIFR External Interrupt Pin Change Interrupt The MCU Control Register - MCUCR Sleep Modes Idle Mode ADC Noise Reduction Mode Power-down Mode Tuneable Internal RC Oscillator The System Clock Oscillator Calibration Register - OSCCAL Internal PLL for Fast Peripheral Clock Generation Timer/Counters The Timer/Counter0 Prescaler The Timer/Counter1 Prescaler The Special Function IO Register - SFIOR The 8-bit Timer/Counter0 The Timer/Counter0 Control Register - TCCR0 The Timer Counter 0 - TCNT0 The 8-bit Timer/Counter1 The Timer/Counter1 Control Register - TCCR1 The Timer/Counter1 - TCNT1 Timer/Counter1 Output Compare RegisterA - OCR1A Timer/Counter1 in PWM Mode Timer/Counter1 Output Compare RegisterB - OCR1B The Watchdog Timer The Watchdog Timer Control Register - WDTCR EEPROM Read/Write Access The EEPROM Address Register - EEAR The EEPROM Data Register - EEDR The EEPROM Control Register - EECR Preventing EEPROM Corruption The Analog Comparator The Analog Comparator Control and Status Register - ACSR The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages Features Operation Prescaling and Conversion Timing ADC Noise Canceler Function The ADC Multiplexer Selection Register - ADMUX The ADC Control and Status Register - ADCSR The ADC Data Register - ADCL and ADCH ADLAR = 0 ADLAR = 1 Scanning Multiple Channels ADC Noise-canceling Techniques ADC Characteristics I/O Port B Unconnected Pins Alternative Functions of Port B The Port B Data Register - PORTB The Port B Data Direction Register - DDRB The Port B Input Pins Address - PINB PORT B as General Digital I/O Alternate Functions of Port B Memory Programming Program and Data Memory Lock Bits Fuse Bits Signature Bytes Calibration Byte Programming the Flash High-voltage Serial Programming High-voltage Serial Programming Algorithm High-voltage Serial Programming Characteristics Low-voltage Serial Downloading Low-voltage Serial Programming Algorithm Data Polling Low-voltage Serial Programming Characteristics Electrical Characteristics Absolute Maximum Ratings DC Characteristics Typical Characteristics ATtiny15L Register Summary ATtiny15L Instruction Set Summary Ordering Information Packaging Information 8P3 8S2 Datasheet revision history Rev H - 09/07 Rev G - 06/07 Rev F - 06/05 Table of Contents