Datasheet AT90CAN32, AT90CAN64, AT90CAN128 - Complete (Atmel) - 5

AT90CAN32/64/128 1.5 Pin Configurations Figure 1-2.
Pinout AT90CAN32/64/128 - TQFP AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4 / TCK) PF5 (ADC5 / TMS) PF6 (ADC6 / TDO) PF7 (ADC7 / TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC(1) 1 48 PA3 (AD3) (RXD0 / PDI) PE0 2 47 PA4 (AD4) INDEX CORNER (TXD0 / PDO) PE1 3 46 PA5 (AD5) (XCK0 / AIN0) PE2 4 45 PA6 (AD6) (OC3A / AIN1) PE3 5 44 PA7 (AD7) (OC3B / INT4) PE4 6 43 PG2 (ALE) (OC3C / INT5) PE5 7 42 PC7 (A15 / CLKO) (T3 / INT6) PE6 8 41 PC6 (A14) (64-lead TQFP top view) (ICP3 / INT7) PE7 9 40 PC5 (A13) (SS) PB0 10 39 PC4 (A12) (SCK) PB1 11 38 PC3 (A11) (MOSI) PB2 12 37 PC2 (A10) (MISO) PB3 13 36 PC1 (A9) (OC2A) PB4 14 35 PC0 (A8) (OC1A) PB5 15 34 PG1 (RD) (OC1B) PB6 16 33 PG0 (WR) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCC GND (2) (2) XTAL2 XTAL1 RESET (T0) PD7 (ICP1) PD4 (TOSC2 ) PG3 (TOSC1 ) PG4 (SCL / INT0) PD0 (SDA / INT1) PD1 (RXD1 / INT2) PD2 (TXD1 / INT3) PD3 (RXCAN / T1) PD6 (OC0A / OC1C) PB7 (TXCAN / XCK1) PD5 NC = Do not connect (May be used in future devices) (1) Timer2 Oscillator (2)
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7679H–CAN–08/08 Document Outline 1. Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 1.2 Part Description 1.3 Disclaimer 1.4 Block Diagram 1.5 Pin Configurations 1.6 Pin Descriptions 2. About Code Examples 3. AVR CPU Core 3.1 Introduction 3.2 Architectural Overview 3.3 ALU - Arithmetic Logic Unit 3.4 Status Register 3.5 General Purpose Register File 3.6 Stack Pointer 3.7 Instruction Execution Timing 3.8 Reset and Interrupt Handling 4. Memories 4.1 In-System Reprogrammable Flash Program Memory 4.2 SRAM Data Memory 4.3 EEPROM Data Memory 4.4 I/O Memory 4.5 External Memory Interface 4.6 General Purpose I/O Registers 5. System Clock 5.1 Clock Systems and their Distribution 5.2 Clock Sources 5.3 Default Clock Source 5.4 Crystal Oscillator 5.5 Low-frequency Crystal Oscillator 5.6 Calibrated Internal RC Oscillator 5.7 External Clock 5.8 Clock Output Buffer 5.9 Timer/Counter2 Oscillator 5.10 System Clock Prescaler 6. Power Management and Sleep Modes 6.1 Idle Mode 6.2 ADC Noise Reduction Mode 6.3 Power-down Mode 6.4 Power-save Mode 6.5 Standby Mode 6.6 Minimizing Power Consumption 7. System Control and Reset 7.1 Reset 7.2 Internal Voltage Reference 7.3 Watchdog Timer 7.4 Timed Sequences for Changing the Configuration of the Watchdog Timer 8. Interrupts 8.1 Interrupt Vectors in AT90CAN32/64/128 8.2 Moving Interrupts Between Application and Boot Space 9. I/O-Ports 9.1 Introduction 9.2 Ports as General Digital I/O 9.3 Alternate Port Functions 9.4 Register Description for I/O-Ports 10. External Interrupts 10.1 External Interrupt Register Description 11. Timer/Counter3/1/0 Prescalers 11.1 Overview 11.2 Timer/Counter0/1/3 Prescalers Register Description 12. 8-bit Timer/Counter0 with PWM 12.1 Features 12.2 Overview 12.3 Timer/Counter Clock Sources 12.4 Counter Unit 12.5 Output Compare Unit 12.6 Compare Match Output Unit 12.7 Modes of Operation 12.8 Timer/Counter Timing Diagrams 12.9 8-bit Timer/Counter Register Description 13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 13.1 Features 13.2 Overview 13.3 Accessing 16-bit Registers 13.4 Timer/Counter Clock Sources 13.5 Counter Unit 13.6 Input Capture Unit 13.7 Output Compare Units 13.8 Compare Match Output Unit 13.9 Modes of Operation 13.10 Timer/Counter Timing Diagrams 13.11 16-bit Timer/Counter Register Description 14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 14.1 Features 14.2 Overview 14.3 Timer/Counter Clock Sources 14.4 Counter Unit 14.5 Output Compare Unit 14.6 Compare Match Output Unit 14.7 Modes of Operation 14.8 Timer/Counter Timing Diagrams 14.9 8-bit Timer/Counter Register Description 14.10 Asynchronous operation of the Timer/Counter2 14.11 Timer/Counter2 Prescaler 15. Output Compare Modulator - OCM 15.1 Overview 15.2 Description 16. Serial Peripheral Interface - SPI 16.1 Features 16.2 SS Pin Functionality 16.3 Data Modes 17. USART (USART0 and USART1) 17.1 Features 17.2 Overview 17.3 Dual USART 17.4 Clock Generation 17.5 Serial Frame 17.6 USART Initialization 17.7 Data Transmission - USART Transmitter 17.8 Data Reception - USART Receiver 17.9 Asynchronous Data Reception 17.10 Multi-processor Communication Mode 17.11 USART Register Description 17.12 Examples of Baud Rate Setting 18. Two-wire Serial Interface 18.1 Features 18.2 Two-wire Serial Interface Bus Definition 18.3 Data Transfer and Frame Format 18.4 Multi-master Bus Systems, Arbitration and Synchronization 18.5 Overview of the TWI Module 18.6 TWI Register Description 18.7 Using the TWI 18.8 Transmission Modes 18.9 Multi-master Systems and Arbitration 19. Controller Area Network - CAN 19.1 Features 19.2 CAN Protocol 19.3 CAN Controller 19.4 CAN Channel 19.5 Message Objects 19.6 CAN Timer 19.7 Error Management 19.8 Interrupts 19.9 CAN Register Description 19.10 General CAN Registers 19.11 MOb Registers 19.12 Examples of CAN Baud Rate Setting 20. Analog Comparator 20.1 Overview 20.2 Analog Comparator Register Description 20.3 Analog Comparator Multiplexed Input 21. Analog to Digital Converter - ADC 21.1 Features 21.2 Operation 21.3 Starting a Conversion 21.4 Prescaling and Conversion Timing 21.5 Changing Channel or Reference Selection 21.6 ADC Noise Canceler 21.7 ADC Conversion Result 21.8 ADC Register Description 22. JTAG Interface and On-chip Debug System 22.1 Features 22.2 Overview 22.3 Test Access Port - TAP 22.4 TAP Controller 22.5 Using the Boundary-scan Chain 22.6 Using the On-chip Debug System 22.7 On-chip Debug Specific JTAG Instructions 22.8 On-chip Debug Related Register in I/O Memory 22.9 Using the JTAG Programming Capabilities 22.10 Bibliography 23. Boundary-scan IEEE 1149.1 (JTAG) 23.1 Features 23.2 System Overview 23.3 Data Registers 23.4 Boundary-scan Specific JTAG Instructions 23.5 Boundary-scan Related Register in I/O Memory 23.6 Boundary-scan Chain 23.7 AT90CAN32/64/128 Boundary-scan Order 23.8 Boundary-scan Description Language Files 24. Boot Loader Support - Read-While-Write Self-Programming 24.1 Features 24.2 Application and Boot Loader Flash Sections 24.3 Read-While-Write and No Read-While-Write Flash Sections 24.4 Boot Loader Lock Bits 24.5 Entering the Boot Loader Program 24.6 Addressing the Flash During Self-Programming 24.7 Self-Programming the Flash 25. Memory Programming 25.1 Program and Data Memory Lock Bits 25.2 Fuse Bits 25.3 Signature Bytes 25.4 Calibration Byte 25.5 Parallel Programming Overview 25.6 Parallel Programming 25.7 SPI Serial Programming Overview 25.8 SPI Serial Programming 25.9 JTAG Programming Overview 26. Electrical Characteristics (1) 26.1 Absolute Maximum Ratings* 26.2 DC Characteristics 26.3 External Clock Drive Characteristics 26.4 Maximum Speed vs. VCC 26.5 Two-wire Serial Interface Characteristics 26.6 SPI Timing Characteristics 26.7 CAN Physical Layer Characteristics 26.8 ADC Characteristics 26.9 External Data Memory Characteristics 26.10 Parallel Programming Characteristics 27. Decoupling Capacitors 28. AT90CAN32/64/128 Typical Characteristics 28.1 Active Supply Current 28.2 Idle Supply Current 28.3 Power-down Supply Current 28.4 Power-save Supply Current 28.5 Standby Supply Current 28.6 Pin Pull-up 28.7 Pin Driver Strength 28.8 Pin Thresholds and Hysteresis 28.9 BOD Thresholds and Analog Comparator Offset 28.10 Internal Oscillator Speed 28.11 Current Consumption of Peripheral Units 28.12 Current Consumption in Reset and Reset Pulse Width 29. Register Summary 30. Instruction Set Summary 31. Ordering Information 32. Packaging Information 32.1 TQFP64 32.2 QFN64 33. Errata 33.1 Errata Summary 33.2 Errata Description 34. Datasheet Revision History for AT90CAN32/64/128 34.1 Changes from 7679G - 03/08 to 7679H - 08/08 34.2 Changes from 7679F - 11/07 to 7679G - 03/08 34.3 Changes from 7679E - 07/07 to 7679F - 11/07 34.4 Changes from 7679D - 02/07 to 7679E - 07/07 34.5 Changes from 7679C - 01/07 to 7679D - 02/07 34.6 Changes from 7679B - 11/06 to 7679C - 01/07 34.7 Changes from 7679A - 10/06 to 7679B - 11/06 34.8 Document Creation