Datasheet ATmega325/V, ATmega3250/V, ATmega645/V, ATmega6450/V - Complete (Atmel) - 10

ATmega325/3250/645/6450 7. AVR CPU Core 7.1 Overview
This section discusses the Atmel® AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
7.2 Architectural Overview Figure 7-1.
Block Diagram of the AVR Architecture Data Bus 8-bit Program Status Flash Counter and Control Program Memory Interrupt 32 x 8 Unit Instruction General Register Purpose SPI Registrers Unit Instruction Watchdog Decoder Timer ALU Analog Control Lines Comparator Direct Addressing Indirect Addressing I/O Module1 Data I/O Module 2 SRAM I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
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2570N–AVR–05/11 Document Outline Features 1. Pin Configurations 2. Overview 2.1 Block Diagram 2.2 Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450 2.3 Pin Descriptions 2.3.1 VCC 2.3.2 GND 2.3.3 Port A (PA7..PA0) 2.3.4 Port B (PB7..PB0) 2.3.5 Port C (PC7..PC0) 2.3.6 Port D (PD7..PD0) 2.3.7 Port E (PE7..PE0) 2.3.8 Port F (PF7..PF0) 2.3.9 Port G (PG5..PG0) 2.3.10 Port H (PH7..PH0) 2.3.11 Port J (PJ6..PJ0) 2.3.12 RESET 2.3.13 XTAL1 2.3.14 XTAL2 2.3.15 AVCC 2.3.16 AREF 3. Resources 4. Data Retention 5. About Code Examples 6. Capacitive touch sensing 7. AVR CPU Core 7.1 Overview 7.2 Architectural Overview 7.3 ALU – Arithmetic Logic Unit 7.4 Status Register 7.4.1 SREG – AVR Status Register 7.5 General Purpose Register File 7.5.1 The X-register, Y-register, and Z-register 7.6 Stack Pointer 7.7 Instruction Execution Timing 7.8 Reset and Interrupt Handling 7.8.1 Interrupt Response Time 8. AVR Memories 8.1 In-System Reprogrammable Flash Program Memory 8.2 SRAM Data Memory 8.2.1 Data Memory Access Times 8.3 EEPROM Data Memory 8.3.1 EEPROM Read/Write Access 8.3.2 EEPROM Write During Power-down Sleep Mode 8.3.3 Preventing EEPROM Corruption 8.4 I/O Memory 8.4.1 General Purpose I/O Registers 8.5 Register Description 8.5.1 EEARH and EEARL – The EEPROM Address Register 8.5.2 EEDR – The EEPROM Data Register 8.5.3 EECR – The EEPROM Control Register 8.5.4 GPIOR2 – General Purpose I/O Register 2 8.5.5 GPIOR1 – General Purpose I/O Register 1 8.5.6 GPIOR0 – General Purpose I/O Register 0 9. System Clock and Clock Options 9.1 Clock Systems and their Distribution 9.1.1 CPU Clock – clkCPU 9.1.2 I/O Clock – clkI/O 9.1.3 Flash Clock – clkFLASH 9.1.4 Asynchronous Timer Clock – clkASY 9.1.5 ADC Clock – clkADC 9.2 Clock Sources 9.2.1 Default Clock Source 9.3 Crystal Oscillator 9.4 Low-frequency Crystal Oscillator 9.5 Calibrated Internal RC Oscillator 9.6 External Clock 9.7 Clock Output Buffer 9.8 Timer/Counter Oscillator 9.9 System Clock Prescaler 9.9.1 Switching Time 9.10 Register Description 9.10.1 OSCCAL – Oscillator Calibration Register 9.10.2 CLKPR – Clock Prescale Register 10. Power Management and Sleep Modes 10.1 Sleep Modes 10.2 Idle Mode 10.3 ADC Noise Reduction Mode 10.4 Power-down Mode 10.5 Power-save Mode 10.6 Standby Mode 10.7 Power Reduction Register 10.8 Minimizing Power Consumption 10.8.1 Analog to Digital Converter 10.8.2 Analog Comparator 10.8.3 Brown-out Detector 10.8.4 Internal Voltage Reference 10.8.5 Watchdog Timer 10.8.6 Port Pins 10.8.7 JTAG Interface and On-chip Debug System 10.9 Register Description 10.9.1 SMCR – Sleep Mode Control Register 10.9.2 PRR – Power Reduction Register 11. System Control and Reset 11.1 Resetting the AVR 11.2 Reset Sources 11.3 Power-on Reset 11.4 External Reset 11.5 Brown-out Detection 11.6 Watchdog Reset 11.7 Internal Voltage Reference 11.7.1 Voltage Reference Enable Signals and Start-up Time 11.8 Watchdog Timer 11.9 Timed Sequences for Changing the Configuration of the Watchdog Timer 11.9.1 Safety Level 1 11.9.2 Safety Level 2 11.10 Register Description 11.10.1 MCUSR – MCU Status Register 11.10.2 WDTCR – Watchdog Timer Control Register 12. Interrupts 12.1 Interrupt Vectors in Atmel ATmega325/3250/645/6450 12.2 Moving Interrupts Between Application and Boot Space 12.3 Register Description 12.3.1 MCUCR – MCU Control Register 13. External Interrupts 13.1 Pin Change Interrupt Timing 13.2 Register Description 13.2.1 EICRA – External Interrupt Control Register A 13.2.2 EIMSK – External Interrupt Mask Register 13.2.3 EIFR – External Interrupt Flag Registe 13.2.4 PCMSK3 – Pin Change Mask Register 3(1) 13.2.5 PCMSK2 – Pin Change Mask Register 2(1) 13.2.6 PCMSK1 – Pin Change Mask Register 1 13.2.7 PCMSK0 – Pin Change Mask Register 0 14. I/O-Ports 14.1 Overview 14.2 Ports as General Digital I/O 14.2.1 Configuring the Pin 14.2.2 Toggling the Pin 14.2.3 Switching Between Input and Output 14.2.4 Reading the Pin Value 14.2.5 Digital Input Enable and Sleep Modes 14.2.6 Unconnected Pins 14.3 Alternate Port Functions 14.3.1 Alternate Functions of Port B 14.3.2 Alternate Functions of Port D 14.3.3 Alternate Functions of Port E 14.3.4 Alternate Functions of Port F 14.3.5 Alternate Functions of Port G 14.3.6 Alternate Functions of Port H 14.3.7 Alternate Functions of Port J 14.4 Register Description 14.4.1 MCUCR – MCU Control Register 14.4.2 PORTA – Port A Data Register 14.4.3 DDRA – Port A Data Direction Register 14.4.4 PINA – Port A Input Pins Address 14.4.5 PORTB – Port B Data Register 14.4.6 DDRB – Port B Data Direction Register 14.4.7 PINB – Port B Input Pins Address 14.4.8 PORTC – Port C Data Register 14.4.9 DDRC – Port C Data Direction Register 14.4.10 PINC – Port C Input Pins Address 14.4.11 PORTD – Port D Data Register 14.4.12 DDRD – Port D Data Direction Register 14.4.13 PIND – Port D Input Pins Address 14.4.14 PORTE – Port E Data Register 14.4.15 DDRE – Port E Data Direction Register 14.4.16 PINE – Port E Input Pins Address 14.4.17 PORTF – Port F Data Register 14.4.18 DDRF – Port F Data Direction Register 14.4.19 PINF – Port F Input Pins Address 14.4.20 PORTG – Port G Data Register 14.4.21 DDRG – Port G Data Direction Register 14.4.22 PING – Port G Input Pins Address 14.4.23 PORTH – Port H Data Register(1) 14.4.24 DDRH – Port H Data Direction Register(1) 14.4.25 PINH – Port H Input Pins Address(1) 14.4.26 PORTJ – Port J Data Register(1) 14.4.27 DDRJ – Port J Data Direction Register(1) 14.4.28 PINJ – Port J Input Pins Address(1) 15. 8-bit Timer/Counter0 with PWM 15.1 Features 15.2 Overview 15.2.1 Definitions 15.2.2 Registers 15.3 Timer/Counter Clock Sources 15.4 Counter Unit 15.5 Output Compare Unit 15.5.1 Force Output Compare 15.5.2 Compare Match Blocking by TCNT0 Write 15.5.3 Using the Output Compare Unit 15.6 Compare Match Output Unit 15.6.1 Compare Output Mode and Waveform Generation 15.7 Modes of Operation 15.7.1 Normal Mode 15.7.2 Clear Timer on Compare Match (CTC) Mode 15.7.3 Fast PWM Mode 15.7.4 Phase Correct PWM Mode 15.8 Timer/Counter Timing Diagrams 15.9 Register Description 15.9.1 TCCR0A – Timer/Counter Control Register A 15.9.2 TCNT0 – Timer/Counter Register 15.9.3 OCR0A – Output Compare Register A 15.9.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register 15.9.5 TIFR0 – Timer/Counter 0 Interrupt Flag Register 16. Timer/Counter0 and Timer/Counter1 Prescalers 16.0.1 Internal Clock Source 16.0.2 Prescaler Reset 16.0.3 External Clock Source 16.1 Register Description 16.1.1 GTCCR – General Timer/Counter Control Register 17. 16-bit Timer/Counter1 17.1 Features 17.2 Overview 17.2.1 Registers 17.2.2 Definitions 17.2.3 Compatibility 17.3 Accessing 16-bit Registers 17.3.1 Reusing the Temporary High Byte Register 17.4 Timer/Counter Clock Sources 17.5 Counter Unit 17.6 Input Capture Unit 17.6.1 Input Capture Trigger Source 17.6.2 Noise Canceler 17.6.3 Using the Input Capture Unit 17.7 Output Compare Units 17.7.1 Force Output Compare 17.7.2 Compare Match Blocking by TCNT1 Write 17.7.3 Using the Output Compare Unit 17.8 Compare Match Output Unit 17.8.1 Compare Output Mode and Waveform Generation 17.9 Modes of Operation 17.9.1 Normal Mode 17.9.2 Clear Timer on Compare Match (CTC) Mode 17.9.3 Fast PWM Mode 17.9.4 Phase Correct PWM Mode 17.9.5 Phase and Frequency Correct PWM Mode 17.10 Timer/Counter Timing Diagrams 17.11 Register Description 17.11.1 TCCR1A – Timer/Counter1 Control Register A 17.11.2 TCCR1B – Timer/Counter1 Control Register B 17.11.3 TCCR1C – Timer/Counter1 Control Register C 17.11.4 TCNT1H and TCNT1L – Timer/Counter1 17.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 17.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B 17.11.7 ICR1H and ICR1L – Input Capture Register 1 17.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register 17.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features 18.2 Overview 18.2.1 Registers 18.2.2 Definitions 18.3 Timer/Counter Clock Sources 18.4 Counter Unit 18.5 Output Compare Unit 18.5.1 Force Output Compare 18.5.2 Compare Match Blocking by TCNT2 Write 18.5.3 Using the Output Compare Unit 18.6 Compare Match Output Unit 18.6.1 Compare Output Mode and Waveform Generation 18.7 Modes of Operation 18.7.1 Normal Mode 18.7.2 Clear Timer on Compare Match (CTC) Mode 18.7.3 Fast PWM Mode 18.7.4 Phase Correct PWM Mode 18.8 Timer/Counter Timing Diagrams 18.9 Asynchronous Operation of Timer/Counter2 18.10 Timer/Counter Prescaler 18.11 Register Description 18.11.1 TCCR2A – Timer/Counter Control Register A 18.11.2 TCNT2 – Timer/Counter Register 18.11.3 OCR2A – Output Compare Register A 18.11.4 ASSR – Asynchronous Status Register 18.11.5 TIMSK2 – Timer/Counter2 Interrupt Mask Register 18.11.6 TIFR2 – Timer/Counter2 Interrupt Flag Register 18.11.7 GTCCR – General Timer/Counter Control Register 19. SPI – Serial Peripheral Interface 19.1 Features 19.2 Overview 19.3 SS Pin Functionality 19.3.1 Slave Mode 19.3.2 Master Mode 19.4 Data Modes 19.5 Register Description 19.5.1 SPCR – SPI Control Register 19.5.2 SPSR – SPI Status Register 19.5.3 SPDR – SPI Data Register 20. USART0 20.1 Features 20.2 Overview 20.2.1 AVR USART vs. AVR UART – Compatibility 20.3 Clock Generation 20.3.1 Internal Clock Generation – The Baud Rate Generator 20.3.2 Double Speed Operation (U2Xn) 20.3.3 External Clock 20.3.4 Synchronous Clock Operation 20.4 Frame Formats 20.4.1 Parity Bit Calculation 20.5 USART Initialization 20.6 Data Transmission – The USART Transmitter 20.6.1 Sending Frames with 5 to 8 Data Bit 20.6.2 Sending Frames with 9 Data Bit 20.6.3 Transmitter Flags and Interrupts 20.6.4 Parity Generator 20.6.5 Disabling the Transmitter 20.7 Data Reception – The USART Receiver 20.7.1 Receiving Frames with 5 to 8 Data Bits 20.7.2 Receiving Frames with 9 Data Bits 20.7.3 Receive Compete Flag and Interrupt 20.7.4 Receiver Error Flags 20.7.5 Parity Checker 20.7.6 Disabling the Receiver 20.7.7 Flushing the Receive Buffer 20.8 Asynchronous Data Reception 20.8.1 Asynchronous Clock Recovery 20.8.2 Asynchronous Data Recovery 20.8.3 Asynchronous Operational Range 20.9 Multi-processor Communication Mode 20.9.1 Using MPCMn 20.10 Examples of Baud Rate Setting 20.11 Register Description 20.11.1 UDRn – USART I/O Data Register n 20.11.2 UCSRnA – USART Control and Status Register n A 20.11.3 UCSRnB – USART Control and Status Register n B 20.11.4 UCSRnC – USART Control and Status Register n C 20.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers 21. USI – Universal Serial Interface 21.1 Overview 21.2 Functional Descriptions 21.2.1 Three-wire Mode 21.2.2 SPI Master Operation Example 21.2.3 SPI Slave Operation Example 21.2.4 Two-wire Mode 21.2.5 Start Condition Detector 21.2.6 Clock speed considerations. 21.3 Alternative USI Usage 21.3.1 Half-duplex Asynchronous Data Transfer 21.3.2 4-bit Counter 21.3.3 12-bit Timer/Counter 21.3.4 Edge Triggered External Interrupt 21.3.5 Software Interrupt 21.4 Register Descriptions 21.4.1 USIDR – USI Data Register 21.4.2 USISR – USI Status Register 21.4.3 USICR – USI Control Register 22. Analog Comparator 22.1 Analog Comparator Multiplexed Input 22.2 Register Description 22.2.1 ADCSRB – ADC Control and Status Register B 22.2.2 ACSR – Analog Comparator Control and Status Register 22.2.3 DIDR1 – Digital Input Disable Register 1 23. Analog to Digital Converter 23.1 Features 23.2 Operation 23.3 Starting a Conversion 23.4 Prescaling and Conversion Timing 23.5 Changing Channel or Reference Selection 23.5.1 ADC Input Channels 23.5.2 ADC Voltage Reference 23.6 ADC Noise Canceler 23.6.1 Analog Input Circuitry 23.6.2 Analog Noise Canceling Techniques 23.6.3 ADC Accuracy Definitions 23.7 ADC Conversion Result 23.8 Register Description 23.8.1 ADMUX – ADC Multiplexer Selection Register 23.8.2 ADCSRA – ADC Control and Status Register A 23.8.3 ADCL and ADCH – The ADC Data Register 23.8.4 ADCSRB – ADC Control and Status Register B 23.8.5 DIDR0 – Digital Input Disable Register 0 24. JTAG Interface and On-chip Debug System 24.1 Features 24.2 Overview 24.3 TAP – Test Access Port 24.4 TAP Controller 24.5 Using the Boundary-scan Chain 24.6 Using the On-chip Debug System 24.7 On-chip Debug Specific JTAG Instructions 24.7.1 PRIVATE0; 0x8 24.7.2 PRIVATE1; 0x9 24.7.3 PRIVATE2; 0xA 24.7.4 PRIVATE3; 0xB 24.8 Using the JTAG Programming Capabilities 24.9 Bibliography 24.10 Register Description 24.10.1 OCDR – On-chip Debug Register 25. IEEE 1149.1 (JTAG) Boundary-scan 25.1 Features 25.2 System Overview 25.3 Data Registers 25.3.1 Bypass Register 25.3.2 Device Identification Register 25.3.3 Reset Register 25.3.4 Boundary-scan Chain 25.4 Boundary-scan Specific JTAG Instructions 25.4.1 EXTEST; 0x0 25.4.2 IDCODE; 0x1 25.4.3 SAMPLE_PRELOAD; 0x2 25.4.4 AVR_RESET; 0xC 25.4.5 BYPASS; 0xF 25.5 Boundary-scan Related Register in I/O Memory 25.5.1 MCUCR – MCU Control Register 25.5.2 MCUSR – MCU Status Register 25.6 Boundary-scan Chain 25.6.1 Scanning the Digital Port Pins 25.6.2 Scanning the RESET Pin 25.6.3 Scanning the Clock Pins 25.6.4 Scanning the Analog Comparator 25.6.5 Scanning the ADC 25.7 Boundary-scan Order 25.8 Boundary-scan Description Language Files 26. Boot Loader Support – Read-While-Write Self-Programming 26.1 Features 26.2 Overview 26.3 Application and Boot Loader Flash Sections 26.3.1 Application Section 26.3.2 BLS – Boot Loader Section 26.4 Read-While-Write and No Read-While-Write Flash Sections 26.4.1 RWW – Read-While-Write Section 26.4.2 NRWW – No Read-While-Write Section 26.5 Boot Loader Lock Bits 26.6 Entering the Boot Loader Program 26.7 Addressing the Flash During Self-Programming 26.8 Self-Programming the Flash 26.8.1 Performing Page Erase by SPM 26.8.2 Filling the Temporary Buffer (Page Loading) 26.8.3 Performing a Page Write 26.8.4 Using the SPM Interrupt 26.8.5 Consideration While Updating BLS 26.8.6 Prevent Reading the RWW Section During Self-Programming 26.8.7 Setting the Boot Loader Lock Bits by SPM 26.8.8 EEPROM Write Prevents Writing to SPMCSR 26.8.9 Reading the Fuse and Lock Bits from Software 26.8.10 Preventing Flash Corruption 26.8.11 Programming Time for Flash when Using SPM 26.8.12 Simple Assembly Code Example for a Boot Loader 26.8.13 Atmel ATmega325/3250/645/6450 Boot Loader Parameters 26.9 Register Description 26.9.1 Store Program Memory Control and Status Register – SPMCSR 27. Memory Programming 27.1 Program And Data Memory Lock Bits 27.2 Fuse Bits 27.2.1 Latching of Fuses 27.3 Signature Bytes 27.4 Calibration Byte 27.5 Parallel Programming Parameters, Pin Mapping, and Commands 27.5.1 Signal Names 27.6 Parallel Programming 27.6.1 Enter Programming Mode 27.6.2 Considerations for Efficient Programming 27.6.3 Chip Erase 27.6.4 Programming the Flash 27.6.5 Programming the EEPROM 27.6.6 Reading the Flash 27.6.7 Reading the EEPROM 27.6.8 Programming the Fuse Low Bits 27.6.9 Programming the Fuse High Bits 27.6.10 Programming the Extended Fuse Bits 27.6.11 Programming the Lock Bits 27.6.12 Reading the Fuse and Lock Bits 27.6.13 Reading the Signature Bytes 27.6.14 Reading the Calibration Byte 27.6.15 Parallel Programming Characteristics 27.7 Serial Downloading 27.7.1 Serial Programming Pin Mapping 27.7.2 Serial Programming Algorithm 27.7.3 Serial Programming Instruction set 27.7.4 SPI Serial Programming Characteristics 27.8 Programming via the JTAG Interface 27.8.1 Programming Specific JTAG Instructions 27.8.2 AVR_RESET (0xC) 27.8.3 PROG_ENABLE (0x4) 27.8.4 PROG_COMMANDS (0x5) 27.8.5 PROG_PAGELOAD (0x6) 27.8.6 PROG_PAGEREAD (0x7) 27.8.7 Data Registers 27.8.8 Reset Register 27.8.9 Programming Enable Register 27.8.10 Programming Command Register 27.8.11 Flash Data Byte Register 27.8.12 Programming Algorithm 27.8.13 Entering Programming Mode 27.8.14 Leaving Programming Mode 27.8.15 Performing Chip Erase 27.8.16 Programming the Flash 27.8.17 Reading the Flash 27.8.18 Programming the EEPROM 27.8.19 Reading the EEPROM 27.8.20 Programming the Fuses 27.8.21 Programming the Lock Bits 27.8.22 Reading the Fuses and Lock Bits 27.8.23 Reading the Signature Bytes 27.8.24 Reading the Calibration Byte 28. Electrical Characteristics 28.1 Absolute Maximum Ratings* 28.2 DC Characteristics 28.3 Speed Grades 28.4 Clock Characteristics 28.4.1 Calibrated Internal Oscillator Accuracy 28.4.2 External Clock Drive Waveforms 28.4.3 External Clock Drive 28.5 System and Reset Characteristics 28.6 SPI Timing Characteristics 28.7 ADC 29. Typical Characteristics 29.1 Active Supply Current 29.2 Idle Supply Current 29.3 Supply Current of I/O modules 29.4 Power-down Supply Current 29.5 Power-save Supply Current 29.6 Standby Supply Current 29.7 Pin Pull-up 29.8 Pin Driver Strength 29.9 Pin Thresholds and hysteresis 29.10 BOD Thresholds and Analog Comparator Offset 29.11 Internal Oscillator Speed 29.12 Current Consumption of Peripheral Units 29.13 Current Consumption in Reset and Reset Pulsewidth 30. Register Summary 31. Instruction Set Summary 32. Ordering Information 32.1 ATmega325 32.2 ATmega3250 32.3 ATmega645 32.4 ATmega6450 33. Packaging Information 33.1 64A 33.2 64M1 33.3 100A 34. Errata 34.1 Errata ATmega325 34.1.1 ATmega325 Rev. C 34.1.2 ATmega325 Rev. B 34.1.3 ATmega325 Rev. A 34.2 Errata ATmega3250 34.2.1 ATmega3250 Rev. C 34.2.2 ATmega3250 Rev. B 34.2.3 ATmega3250 Rev. A 34.3 Errata ATmega645 34.3.1 ATmega645 Rev. A 34.4 Errata ATmega6450 34.4.1 ATmega6450 Rev. A 35. Datasheet Revision History 35.1 Rev. 2570N – 05/11 35.2 Rev. 2570M – 04/11 35.3 Rev. 2570L – 08/07 35.4 Rev. 2570K – 04/07 35.5 Rev. 2570J – 11/06 35.6 Rev. 2570I – 07/06 35.7 Rev. 2570H – 06/06 35.8 Rev. 2570G – 04/06 35.9 Rev. 2570F – 03/06 35.10 Rev. 2570E – 03/06 35.11 Rev. 2570D – 05/05 35.12 Rev. 2570C – 11/04 35.13 Rev. 2570B – 09/04 35.14 Rev. 2570A – 09/04 Table of Contents