Datasheet AT90PWM216, AT90PWM316 - Complete (Atmel) - 7

3.1 Block Diagram Figure 3-1.
Block Diagram Data Bus 8-bit Program Status Interrupt 16Kx8 Flash Counter and Control Unit Program Memory SPI Unit 32 x 8 Instruction General Watchdog Register Purpose Timer Registrers 3 Analog Instruction Comparators Decoder ALU DALI USART ressing Control Lines Timer 0 Direct Add Indirect Addressing Timer 1 Data SRAM 1024 bytes ADC EEPROM 512 bytes DAC I/O Lines PSC 2/1/0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90PWM216/316 provides the following features: 16K bytes of In-System Programmable Flash with Read- While-Write capabilities, 512 bytes EEPROM, 1024 bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, three Power Stage Controllers, two flexible Timer/Counters with compare modes and PWM, one USART with DALI mode, an 11-channel 10-bit ADC with two differential input stage with programmable gain, a 10- bit DAC, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt system to con- tinue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Res- AT90PWM216/316 [DATASHEET] 7 7710H–AVR–07/2013 Document Outline Features 1. Disclaimer 2. Pin Configurations 2.1 Pin Descriptions 3. Overview 3.1 Block Diagram 3.2 Pin Descriptions 3.3 About Code Examples 4. AVR CPU Core 4.1 Introduction 4.2 Architectural Overview 4.3 ALU – Arithmetic Logic Unit 4.4 Status Register 4.5 General Purpose Register File 4.6 Stack Pointer 4.7 Instruction Execution Timing 4.8 Reset and Interrupt Handling 5. Memories 5.1 In-System Reprogrammable Flash Program Memory 5.2 SRAM Data Memory 5.3 EEPROM Data Memory 5.4 I/O Memory 5.5 General Purpose I/O Registers 6. System Clock 6.1 Clock Systems and their Distribution 6.2 Clock Sources 6.3 Default Clock Source 6.4 Low Power Crystal Oscillator 6.5 Calibrated Internal RC Oscillator 6.6 PLL 6.7 128 kHz Internal Oscillator 6.8 External Clock 6.9 Clock Output Buffer 6.10 System Clock Prescaler 7. Power Management and Sleep Modes 7.1 Idle Mode 7.2 ADC Noise Reduction Mode 7.3 Power-down Mode 7.4 Standby Mode 7.5 Power Reduction Register 7.6 Minimizing Power Consumption 8. System Control and Reset 8.1 Resetting the AVR 8.2 Reset Sources 8.3 Power-on Reset 8.4 External Reset 8.5 Brown-out Detection 8.6 Watchdog Reset 8.7 MCU Status Register – MCUSR 8.8 Internal Voltage Reference 8.9 Watchdog Timer 9. Interrupts 9.1 Interrupt Vectors in AT90PWM216/316 10. I/O-Ports 10.1 Introduction 10.2 Ports as General Digital I/O 10.3 Alternate Port Functions 10.4 Register Description for I/O-Ports 11. External Interrupts 12. Timer/Counter0 and Timer/Counter1 Prescalers 13. 8-bit Timer/Counter0 with PWM 13.1 Overview 13.2 Timer/Counter Clock Sources 13.3 Counter Unit 13.4 Output Compare Unit 13.5 Compare Match Output Unit 13.6 Modes of Operation 13.7 Timer/Counter Timing Diagrams 13.8 8-bit Timer/Counter Register Description 14. 16-bit Timer/Counter1 with PWM 14.1 Overview 14.2 Accessing 16-bit Registers 14.3 Timer/Counter Clock Sources 14.4 Counter Unit 14.5 Input Capture Unit 14.6 Output Compare Units 14.7 Compare Match Output Unit 14.8 Modes of Operation 14.9 Timer/Counter Timing Diagrams 14.10 16-bit Timer/Counter Register Description 15. Power Stage Controller – (PSC0, PSC1 & PSC2) 15.1 Features 15.2 Overview 15.3 PSC Description 15.4 Signal Description 15.5 Functional Description 15.6 Update of Values 15.7 Enhanced Resolution 15.8 PSC Inputs 15.9 PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait 15.10 PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait 15.11 PSC Input Mode 3: Stop signal, Execute Opposite while Fault active 15.12 PSC Input Mode 4: Deactivate outputs without changing timing. 15.13 PSC Input Mode 5: Stop signal and Insert Dead-Time 15.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. 15.15 PSC Input Mode 7: Halt PSC and Wait for Software Action 15.16 PSC Input Mode 8: Edge Retrigger PSC 15.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC 15.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output 15.19 PSC2 Outputs 15.20 Analog Synchronization 15.21 Interrupt Handling 15.22 PSC Synchronization 15.23 PSC Clock Sources 15.24 Interrupts 15.25 PSC Register Definition 15.26 PSC2 Specific Register 16. Serial Peripheral Interface – SPI 16.1 Features 16.2 SS Pin Functionality 16.3 Data Modes 17. USART 17.1 Features 17.2 Overview 17.3 Clock Generation 17.4 Serial Frame 17.5 USART Initialization 17.6 Data Transmission – USART Transmitter 17.7 Data Reception – USART Receiver 17.8 Asynchronous Data Reception 17.9 Multi-processor Communication Mode 17.10 USART Register Description 17.11 Examples of Baud Rate Setting 18. EUSART (Extended USART) 18.1 Features 18.2 Overview 18.3 Serial Frames 18.4 Configuring the EUSART 18.5 Data Reception – EUSART Receiver 18.6 EUSART Registers Description 19. Analog Comparator 19.1 Overview 19.2 Analog Comparator Register Description 20. Analog to Digital Converter - ADC 20.1 Features 20.2 Operation 20.3 Starting a Conversion 20.4 Prescaling and Conversion Timing 20.5 Changing Channel or Reference Selection 20.6 ADC Noise Canceler 20.7 ADC Conversion Result 20.8 ADC Register Description 20.9 Amplifier 20.10 Amplifier Control Registers 21. Digital to Analog Converter - DAC 21.1 Features 21.2 Operation 21.3 Starting a Conversion 21.4 DAC Register Description 22. debugWIRE On-chip Debug System 22.1 Features 22.2 Overview 22.3 Physical Interface 22.4 Software Break Points 22.5 Limitations of debugWIRE 22.6 debugWIRE Related Register in I/O Memory 23. Boot Loader Support – Read-While-Write Self-Programming 23.1 Boot Loader Features 23.2 Application and Boot Loader Flash Sections 23.3 Read-While-Write and No Read-While-Write Flash Sections 23.4 Boot Loader Lock Bits 23.5 Entering the Boot Loader Program 23.6 Addressing the Flash During Self-Programming 23.7 Self-Programming the Flash 24. Memory Programming 24.1 Program And Data Memory Lock Bits 24.2 Fuse Bits 24.3 PSC Output Behavior During Reset 24.4 Signature Bytes 24.5 Calibration Byte 24.6 Parallel Programming Parameters, Pin Mapping, and Commands 24.7 Serial Programming Pin Mapping 24.8 Parallel Programming 24.9 Serial Downloading 25. Electrical Characteristics 25.1 Absolute Maximum Ratings* 25.2 DC Characteristics 25.3 External Clock Drive Characteristics 25.4 Maximum Speed vs. VCC 25.5 PLL Characteristics. 25.6 SPI Timing Characteristics 25.7 ADC Characteristics 25.8 DAC Characteristics 25.9 Parallel Programming Characteristics 26. Typical Characteristics – Preliminary Data 26.1 Active Supply Current 26.2 Idle Supply Current 26.3 Power-Down Supply Current 26.4 Standby Supply Current 26.5 Pin Pull-up 26.6 Pin Driver Strength 26.7 Pin Thresholds and Hysteresis 26.8 BOD Thresholds and Analog Comparator Offset 26.9 Analog Reference 26.10 Internal Oscillator Speed 26.11 Current Consumption of Peripheral Units 26.12 Current Consumption in Reset and Reset Pulse width 27. Register Summary 28. Instruction Set Summary 29. Ordering Information 30. Package Information 30.1 SO24 30.2 SO32 30.3 QFN32 31. Errata AT90PWM216/316 31.1 Revision C 31.2 Revision B 31.3 Revision A 32. Datasheet Revision History for AT90PWM216/316 32.1 Rev. 7710H – 07/2013 32.2 Rev. 7710G – 03/2013 32.3 Rev. 7710F – 09/11 32.4 Rev. 7710E – 08/10 32.5 Rev. 7710D 32.6 Rev. 7710C 32.7 Rev. 7710B 32.8 Rev. 7710A Table of Contents