Datasheet ATmega8515, ATmega8515L (Atmel) - 4

link to page 53 link to page 53 link to page 137 link to page 137 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8515 provides the following features: 8K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, an External memory interface, 35 general purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with compare modes, Internal and External inter- rupts, a Serial Programmable USART, a programmable Watchdog Timer with internal Oscillator, a SPI serial port, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and Interrupt system to continue functioning. The Power-down mode saves the Register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hard- ware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-chip ISP Flash allows the Program memory to be reprogrammed In-System through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Soft- ware in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega8515 is supported with a full suite of program and system development tools including: C Compilers, Macro assemblers, Program debugger/simulators, In-cir- cuit Emulators, and Evaluation kits.
Disclaimer
Typical values contained in this datasheet are based on simulations and characteriza- tion of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
AT90S4414/8515 and
The ATmega8515 provides all the features of the AT90S4414/8515. In addition, several
ATmega8515
n e w f e a t u r e s a r e a d d e d . T h e A T m e g a 8 5 1 5 i s b a c k w a r d c o m p a t i b l e w i t h
Compatibility
AT90S4414/8515 in most cases. However, some incompatibilities between the two microcontrollers exist. To solve this problem, an AT90S4414/8515 compatibility mode can be selected by programming the S8515C Fuse. ATmega8515 is 100% pin compati- ble with AT90S4414/8515, and can replace the AT90S4414/8515 on current printed circuit boards. However, the location of Fuse bits and the electrical characteristics dif- fers between the two devices.
AT90S4414/8515 Compatibility
Programming the S8515C Fuse will change the following functionality:
Mode
• The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 53 for details. • The double buffering of the USART Receive Registers is disabled. See “AVR USART vs. AVR UART – Compatibility” on page 137 for details. • PORTE(2:1) will be set as output, and PORTE0 will be set as input.
4 ATmega8515(L)
2512K–AVR–01/10 Document Outline Features Pin Configurations Overview Block Diagram Disclaimer AT90S4414/8515 and ATmega8515 Compatibility AT90S4414/8515 Compatibility Mode Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E(PE2..PE0) RESET XTAL1 XTAL2 Resources About Code Examples AVR CPU Core Introduction Architectural Overview ALU – Arithmetic Logic Unit Status Register General Purpose Register File The X-register, Y-register, and Z-register Stack Pointer Instruction Execution Timing Reset and Interrupt Handling Interrupt Response Time AVR ATmega8515 Memories In-System Reprogrammable Flash Program memory SRAM Data Memory Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access The EEPROM Address Register – EEARH and EEARL The EEPROM Data Register – EEDR The EEPROM Control Register – EECR EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption I/O Memory External Memory Interface Overview Using the External Memory Interface Address Latch Requirements Pull-up and Bus Keeper Timing XMEM Register Description MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR Special Function IO Register – SFIOR Using all Locations of External Memory Smaller than 64 KB Using all 64KB Locations of External Memory System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clkCPU I/O Clock – clkI/O Flash Clock – clkFLASH Clock Sources Default Clock Source Crystal Oscillator Low-frequency Crystal Oscillator External RC Oscillator Calibrated Internal RC Oscillator Oscillator Calibration Register – OSCCAL External Clock Power Management and Sleep Modes MCU Control Register – MCUCR MCU Control and Status Register – MCUCSR Extended MCU Control Register – EMCUCR Idle Mode Power-down Mode Standby Mode Minimizing Power Consumption Analog Comparator Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins System Control and Reset Resetting the AVR Reset Sources Power-on Reset External Reset Brown-out Detection Watchdog Reset MCU Control and Status Register – MCUCSR Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time Watchdog Timer Watchdog Timer Control Register – WDTCR Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 0 Safety Level 1 Safety Level 2 Interrupts Interrupt Vectors in ATmega8515 Moving Interrupts between Application and Boot Space General Interrupt Control Register – GICR I/O Ports Introduction Ports as General Digital I/O Configuring the Pin Reading the Pin Value Digital Input Enable and Sleep Modes Unconnected pins Alternate Port Functions Special Function IO Register – SFIOR Alternate Functions of Port A Alternate Functions Of Port B Alternate Functions of Port C Alternate Functions of Port D Alternate Functions of Port E Register Description for I/O Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input Pins Address – PINB Port C Data Register – PORTC Port C Data Direction Register – DDRC Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE Port E Input Pins Address – PINE External Interrupts MCU Control Register – MCUCR Extended MCU Control Register – EMCUCR General Interrupt Control Register – GICR General Interrupt Flag Register – GIFR 8-bit Timer/Counter0 with PWM Overview Registers Definitions Timer/Counter Clock Sources Counter Unit Output Compare Unit Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Timer/Counter Timing Diagrams 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 Timer/Counter Register – TCNT0 Output Compare Register – OCR0 Timer/Counter Interrupt Mask Register – TIMSK Timer/Counter Interrupt Flag Register – TIFR Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source Special Function IO Register – SFIOR 16-bit Timer/Counter1 Overview Registers Definitions Compatibility Accessing 16-bit Registers Reusing the Temporary High Byte Register Timer/Counter Clock Sources Counter Unit Input Capture Unit Input Capture Trigger Source Noise Canceler Using the Input Capture Unit Output Compare Units Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit Compare Match Output Unit Compare Output Mode and Waveform Generation Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode Phase and Frequency Correct PWM Mode Timer/Counter Timing Diagrams 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A Timer/Counter1 Control Register B – TCCR1B Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Input Capture Register 1 – ICR1H and ICR1L Timer/Counter Interrupt Mask Register – TIMSK(1) Timer/Counter Interrupt Flag Register – TIFR(1) Serial Peripheral Interface – SPI SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR SPI Status Register – SPSR SPI Data Register – SPDR Data Modes USART Single USART AVR USART vs. AVR UART – Compatibility Clock Generation Internal Clock Generation – The Baud Rate Generator Double Speed Operation (U2X) External Clock Synchronous Clock Operation Frame Formats Parity Bit Calculation USART Initialization Data Transmission – The USART Transmitter Sending Frames with 5 to 8 Data Bits Sending Frames with 9 Data Bits Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter Data Reception – The USART Receiver Receiving Frames with 5 to 8 Data Bits Receiving Frames with 9 Data Bits Receive Compete Flag and Interrupt Receiver Error Flags Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception Asynchronous Clock Recovery Asynchronous Data Recovery Asynchronous Operational Range Multi-processor Communication Mode Using MPCM Accessing UBRRH/UCSRC Registers Write Access Read Access USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA USART Control and Status Register B – UCSRB USART Control and Status Register C – UCSRC USART Baud Rate Registers – UBRRL and UBRRH Examples of Baud Rate Setting Analog Comparator Analog Comparator Control and Status Register – ACSR Boot Loader Support – Read-While-Write Self-Programming Features Application and Boot Loader Flash Sections Application Section BLS – Boot Loader Section Read-While-Write and No Read-While-Write Flash Sections RWW – Read-While-Write Section NRWW – No Read-While-Write Section Boot Loader Lock bits Entering the Boot Loader Program Store Program memory Control Register – SPMCR Addressing the Flash During Self- Programming Self-Programming the Flash Performing Page Erase by SPM Filling the Temporary Buffer (page loading) Performing a Page Write Using the SPM Interrupt Consideration While Updating BLS Prevent Reading the RWW Section During Self- Programming Setting the Boot Loader Lock bits by SPM EEPROM Write Prevents Writing to SPMCR Reading the Fuse and Lock bits from Software Preventing Flash Corruption Programming Time for Flash when using SPM Simple Assembly Code Example for a Boot Loader ATmega8515 Boot Loader Parameters Memory Programming Program and Data Memory Lock bits Fuse bits Latching of Fuses Signature Bytes Calibration Byte Parallel Programming Parameters, Pin Mapping, and Commands Signal Names Parallel Programming Enter Programming Mode Considerations for Efficient Programming Chip Erase Programming the Flash Programming the EEPROM Reading the Flash Reading the EEPROM Programming the Fuse Low Bits Programming the Fuse High Bits Programming the Lock bits Reading the Fuse and Lock bits Reading the Signature Bytes Reading the Calibration Byte Parallel Programming Characteristics Serial Downloading Serial Programming Pin Mapping Serial Programming Algorithm Data Polling Flash Data Polling EEPROM Electrical Characteristics Absolute Maximum Ratings* External Clock Drive Waveforms External Clock Drive SPI Timing Characteristics External Data Memory Timing ATmega8515 Typical Characteristics Active Supply Current Idle Supply Current Power-Down Supply Current Standby Supply Current Pin Pull-up Pin Driver Strength Pin Thresholds And Hysteresis BOD Thresholds And Analog Comparator Offset Internal Oscillator Speed Current Consumption Of Peripheral Units Current Consumption In Reset And Reset Pulsewidth Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 40P6 44J 44M1 Errata ATmega8515(L) Rev. C and D Datasheet Revision History Changes from Rev. 2512J-10/06 to Rev. 2512K-01/10 Changes from Rev. 2512I-08/06 to Rev. 2512J-10/06 Changes from Rev. 2512H-04/06 to Rev. 2512I-08/06 Changes from Rev. 2512G-03/05 to Rev. 2512H-04/06 Changes from Rev. 2512F-12/03 to Rev. 2512G-03/05 Rev. 2512E-09/03 Rev. 2512E-09/03 Rev. 2512D-02/03 Rev. 2512C-10/02 Rev. 2512B-09/02 Rev. 2512A-04/02 Table of Contents