Datasheet LTC1698 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Isolated Secondary Synchronous Rectifier Controller |
| Seiten / Seite | 24 / 10 — APPLICATIO S I FOR ATIO. Undervoltage Lockout. SYNC Input. VDD Regulator. … |
| Dateiformat / Größe | PDF / 1.1 Mb |
| Dokumentensprache | Englisch |
APPLICATIO S I FOR ATIO. Undervoltage Lockout. SYNC Input. VDD Regulator. Figure 3. Synchronization Using Pulse Transformer
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LTC1698
U U W U APPLICATIO S I FOR ATIO Undervoltage Lockout
supply requirement. Under start-up conditions, it must be small enough to power up instantaneously, enabling the In UVLO (low VDD voltage) the drivers FG and CG are shut LTC1698 to regulate the feedback loop. Using a larger off and the pins OPTODRV, VAUX, PWRGD and ICOMP are capacitor requires evaluation of the start-up performance. forced low. The LTC1698 allows the bandgap and the internal bias currents to reach their steady-state values
SYNC Input
before releasing UVLO. Typically, this happens when VDD reaches approximately 4.0V. Beyond this threshold, the Figure 3 shows the synchronous forward converter appli- drivers start switching. The OPTODRV, V cation. The primary controller LT3781 runs at a fixed AUX, PWRGD and I frequency and controls MOSFETs Q1 and Q2. The second- COMP pins return to their normal values and the chip is fully functional. However, if the V ary controller LTC1698 controls MOSFETs Q3 and Q4. An DD voltage is less than 7V, the OPTODRV and V inexpensive, small-size pulse transformer T2 synchro- AUX current sourcing capabilities are limited. See the OPTO driver graphs in the Typical Perfor- nizes the primary and the secondary controllers. Figure 4 mance Characteristics section. shows the pulse transformer timing waveforms. When the LT3781 synchronization output SG goes low, MOSFET
VDD Regulator
L1 The bias supply for the LTC1698 is generated by peak VOUT Q1 rectifying the isolated transformer secondary winding. As TG Q4 CG shown in Figure 2, the zener diode Z1 is connected from • • base of Q5 to ground such that the emitter of Q5 is D1 PRIMARY SECONDARY VIN CONTROLLER T1 CONTROLLER COUT regulated to one diode drop below the zener voltage. RZ is LT3781 D2 LTC1698 selected to bring Z1 into conduction and also provide base current to Q5. A resistor (on the order of a few hundred Q2 Q3 SG BG FG SYNC ohms), in series with the base of Q5, may be required to surpress high frequency oscillations depending on Q5’s 1698 F03 • • selection. A power MOSFET can also be used by increasing CSG CSYNC T2 the zener diode value to offset the drop of the gate-to- RSYNC source voltage. VDD supply current varies linearly with the supply voltage, driver load and clock frequency. A 4.7µF PRIMARY SECONDARY bypass capacitor for the VDD supply is sufficient for most ISOLATION BARRIER applications. This capacitor must be large enough to
Figure 3. Synchronization Using Pulse Transformer
provide a stable DC voltage to meet the LTC1698 VDD V TG SECONDARY BG 1Ω SG D3 RZ 2k SYNC RB* Q5 0.47µF FZT690 Z1 VDD 10V FG 4.7µF CG *RB IS OPTIONAL, SEE TEXT 1698 F04 1698 F02
Figure 4. Primary Side and Secondary Side Figure 2. VDD Regulator Synchronization Waveforms
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U U W U APPLICATIO S I FOR ATIO Undervoltage Lockout
supply requirement. Under start-up conditions, it must be small enough to power up instantaneously, enabling the In UVLO (low VDD voltage) the drivers FG and CG are shut LTC1698 to regulate the feedback loop. Using a larger off and the pins OPTODRV, VAUX, PWRGD and ICOMP are capacitor requires evaluation of the start-up performance. forced low. The LTC1698 allows the bandgap and the internal bias currents to reach their steady-state values
SYNC Input
before releasing UVLO. Typically, this happens when VDD reaches approximately 4.0V. Beyond this threshold, the Figure 3 shows the synchronous forward converter appli- drivers start switching. The OPTODRV, V cation. The primary controller LT3781 runs at a fixed AUX, PWRGD and I frequency and controls MOSFETs Q1 and Q2. The second- COMP pins return to their normal values and the chip is fully functional. However, if the V ary controller LTC1698 controls MOSFETs Q3 and Q4. An DD voltage is less than 7V, the OPTODRV and V inexpensive, small-size pulse transformer T2 synchro- AUX current sourcing capabilities are limited. See the OPTO driver graphs in the Typical Perfor- nizes the primary and the secondary controllers. Figure 4 mance Characteristics section. shows the pulse transformer timing waveforms. When the LT3781 synchronization output SG goes low, MOSFET
VDD Regulator
L1 The bias supply for the LTC1698 is generated by peak VOUT Q1 rectifying the isolated transformer secondary winding. As TG Q4 CG shown in Figure 2, the zener diode Z1 is connected from • • base of Q5 to ground such that the emitter of Q5 is D1 PRIMARY SECONDARY VIN CONTROLLER T1 CONTROLLER COUT regulated to one diode drop below the zener voltage. RZ is LT3781 D2 LTC1698 selected to bring Z1 into conduction and also provide base current to Q5. A resistor (on the order of a few hundred Q2 Q3 SG BG FG SYNC ohms), in series with the base of Q5, may be required to surpress high frequency oscillations depending on Q5’s 1698 F03 • • selection. A power MOSFET can also be used by increasing CSG CSYNC T2 the zener diode value to offset the drop of the gate-to- RSYNC source voltage. VDD supply current varies linearly with the supply voltage, driver load and clock frequency. A 4.7µF PRIMARY SECONDARY bypass capacitor for the VDD supply is sufficient for most ISOLATION BARRIER applications. This capacitor must be large enough to
Figure 3. Synchronization Using Pulse Transformer
provide a stable DC voltage to meet the LTC1698 VDD V TG SECONDARY BG 1Ω SG D3 RZ 2k SYNC RB* Q5 0.47µF FZT690 Z1 VDD 10V FG 4.7µF CG *RB IS OPTIONAL, SEE TEXT 1698 F04 1698 F02
Figure 4. Primary Side and Secondary Side Figure 2. VDD Regulator Synchronization Waveforms
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