Datasheet ADM1041A (Analog Devices) - 7

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ADM1041A Parameter Min Typ Max Unit Test Conditions/Comments
LOCAL VOLTAGE SENSE, VLS, See Figure 9. AND FALSE UV CLAMP Input Voltage Range3 2.3 (VDD – 2) V Set by external resistor divider. Stage Gain 1.3 At VLS = 1.8 V False UV Clamp, VLS, Input Voltage Nominal, 1.3 1.85 2.1 V and Trim Range Clamp Trim Step 0.2 % VRANGE Clamp Trim Step 3.1 mV 8 bits, 255 steps, Reg 18h[7:0]. See Table 33. Local Overvoltage 1.9 2.4 2.85 V Nominal and Trim Range OV Trim Step 0.15 % VRANGE OV Trim Step 3.7 mV 8 bits, 255 steps Reg 0Ah[7:0]. See Table 19. Noise Filter, for OVP Function Only 5 25 μs Local Undervoltage 1.3 1.7 2.1 V Nominal and Trim Range UV Trim Step 0.18 % VRANGE UV Trim Step 3.1 mV 8 bits, 255 steps, Reg 09h[7:0]. See Table 18. Noise Filter, for UVP Function Only 300 600 μs VOLTAGE ERROR AMPLIFIER, VCMP See Figure 15. Reference Voltage VREF_SOFT_START 1.49 1.51 V TA = 25°C Temperature Stability2 ±100 μV/°C −40°C ≤ TA ≤ 85°C Long-Term Voltage Stability2 ±0.2 % Over 1,000 hr, TJ = 125°C Soft-Start Period Range 0 40 ms Ramp is 7 bit, 127 steps Set Soft-Start Period 300 μs Reg 10h[3:2] = 00. See Table 25. 10 ms Reg 10h[3:2] = 01. See Table 25. 20 ms Reg 10h[3:2] = 10. See Table 25. 40 ms Reg 10h[3:2] = 11. See Table 25. Unity Gain Bandwidth, GBW 1 MHz See Figure 11. Transconductance 1.9 2.7 3.5 mA/V At IVCMP = ±180 μA Source Current 250 μA At VVCMP > 1 V Sink Current 250 μA At VVCMP < VDD − 1 V DIFFERENTIAL CURRENT SENSE INPUT, Reg 17h[7] = 0. See Table 18. CS−, CS+ ISENSE mode. See Figure 13. Common-Mode Range 0 (VDD – 2) V Set by external divider External Divider Tolerance Trim Range −5 mV Reg 16h[5:3] = 000. See Table 31. (With Respect to Input) −10 mV Reg 16h[5:3] = 001. See Table 31. −20 mV Reg 16h[5:3] = 010. See Table 31. 5 mV Reg 16h[5:3] = 100. See Table 31. 10 mV Reg 16h[5:3] = 101. See Table 31. 20 mV Reg 16h[5:3] = 110. See Table 31. External Divider Tolerance Trim Step Size 20 μV VCM = 2.0 V (With Respect to Input) 39 μV 8 bits, 255 steps 78 μV Reg 14h[7:0]. See Table 29. Rev. 0 | Page 7 of 56 Document Outline FEATURES SECONDARY-SIDE FEATURES INTERFACE AND INTERNAL FEATURES APPLICATIONS GENERAL DESCRIPTION SAMPLE APPLICATION CIRCUIT DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY THEORY OF OPERATION POWER MANAGEMENT GAIN TRIMMING AND CONFIGURATION DIFFERENTIAL REMOTE SENSE AMPLIFIER SET LOAD VOLTAGE LOAD OVERVOLTAGE (OV) LOCAL VOLTAGE SENSE LOCAL OVERVOLTAGE PROTECTION (OVP) LOCAL UNDERVOLTAGE PROTECTION (UVP) FALSE UV CLAMP VOLTAGE ERROR AMPLIFIER MAIN VOLTAGE REFERENCE CURRENT-SENSE AMPLIFIER CURRENT SENSING CURRENT-TRANSFORMER INPUT CURRENT-SENSE CALIBRATION CURRENT-LIMIT ERROR AMPLIFIER OVERCURRENT PROTECTION CURRENT SHARE CURRENT-SHARE OFFSET ISHARE DRIVE AMPLIFIER DIFFERENTIAL SENSE AMPLIFIER ISHARE ERROR AMPLIFIER ISHARE CLAMP SHARE_OK DETECTOR PULSE/ACSENSE2 PULSE ACSENSE OrFET GATE DRIVE OSCILLATOR AND TIMING GENERATORS LOGIC I/O AND MONITOR PINS CBD/ALERT MON1 MON2 PEN PSON MON3 DC_OK (POWER-OK, POWER Good, Etc.) MON4 AC_OK MON5 SMBus SERIAL PORT MICROPROCESSOR SUPPORT Interfacing Configuring for a Microprocessor BROADCASTING SMBus SERIAL INTERFACE GENERAL SMBus TIMING SMBus PROTOCOLS FOR RAM AND EEPROM SMBus Erase EEPROM Page Operations SMBus Write Operations Send Byte Write Byte/Word Block Write SMBus READ OPERATIONS Receive Byte Block Read Notes on SMBus Read Operations SMBus ALERT RESPONSE ADDRESS (ARA) SUPPORT FOR SMBus 1.1 LAYOUT CONSIDERATIONS POWER-UP AUTO-CONFIGURATION EXTENDED SMBus ADDRESSING SDA/PSONLINK SCL/AC_OKLink BACKDOOR ACCESS REGISTER LISTING DETAILED REGISTER DESCRIPTIONS MANUFACTURING DATA MICROPROCESSOR SUPPORT TEST NAME TABLE OUTLINE DIMENSIONS ORDERING GUIDE