Datasheet LT1725 (Analog Devices) - 6

LT1725
U U U PI FU CTIO S PGND (Pin 1):
The power ground pin carries the GATE third winding transformer turns ratio is the primary deter- node discharge current. This is typically a current spike of minant of the output voltage. The Thevenin equivalent several hundred mA with a duration of tens of nanosec- resistance of the feedback divider should be roughly 3k. onds. It should be connected directly to a good quality See Applications Information for more details. ground plane.
3VOUT (Pin 9):
Output pin for nominal 3V reference. This
ISENSE (Pin 2):
Pin to measure switch current with exter- facilitates various user applications. This node is internally nal sense resistor. The sense resistor should be of a current limited for protection and is intended to drive noninductive construction as high speed performance is either moderate capacitive loads of several hundred pF or essential. Proper grounding technique is also required to less, or, very large capacitive loads of 0.1µF or more. See avoid distortion of the high speed current waveform. A Applications Information for more details. preset internal limit of nominally 250mV at this pin effects
UVLO (Pin 10):
This pin allows the use of an optional a switch current limit. external resistor divider to set an undervoltage lockout
SFST (Pin 3):
Pin for optional external capacitor to effect based upon VIN (not VCC) level. (Note: If the VCC voltage is soft-start function. See Applications Information for details. sufficient to allow the part to start up, but the UVLO pin is held below its threshold, output switching action will be
ROCMP (Pin 4):
Input pin for optional external load compen- disabled, but the part will draw its normal quiescent sation resistor. Use of this pin allows nominal compensa- current from V tion for nonzero output impedance in the power transformer CC. This typically causes a benign relaxation oscillation action on the V secondary circuit, including secondary winding impedance, CC pin in the conventional “trickle-charge” bootstrapped configuration.) output Schottky diode impedance and output capacitor ESR. In less demanding applications, this resistor is not The bias current on this pin is a function of the state of the needed. See Applications Information for more details. UVLO comparator; as the threshold is exceeded, the bias current increases. This creates a hysteresis band equal to
RCMPC (Pin 5):
Pin for external filter capacitor for optional the change in bias current times the Thevenin impedance load compensation function. A common 0.1µF ceramic of the user’s resistive divider. The user may thereby adjust capacitor will suffice for most applications. See Applica- the impedance of the UVLO divider to achieve a desired tions Information for further details. degree of hysteresis. A 100pF capacitor to ground is
OSCAP (Pin 6):
Pin for external timing capacitor to set recommended on this pin. See Applications Information oscillator switching frequency. See Applications Informa- for details. tion for details.
SGND (Pin 11):
The signal ground pin is a clean ground.
VC (pin 7):
This is the control voltage pin which is the The internal reference, oscillator and feedback amplifier output of the feedback amplifier and the input of the are referred to it. Keep the ground path connection to the current comparator. Frequency compensation of the FB pin, OSCAP capacitor and the VC compensation capaci- overall loop is effected in most cases by placing a capaci- tor free of large ground currents. tor between this node and ground.
MINENAB (Pin 12):
Pin for external programming resistor
FB (Pin 8):
Input pin for external “feedback” resistor to set minimum enable time. See Applications Information divider. The ratio of this divider, times the internal for details. bandgap (VBG) reference, times the effective output-to- 1725fa 6