Datasheet LTC1871-7 (Analog Devices) - 9

LTC1871-7
operaTion
In applications where fixed frequency operation is more inductor current is 20% of its maximum value) followed critical than low current efficiency, or where the lowest by long periods of sleep will be observed, thereby greatly output ripple is desired, pulse-skip mode operation should improving converter efficiency. Oscilloscope waveforms be used and the MODE/SYNC pin should be connected illustrating Burst Mode operation are shown in Figure 3. to the INTVCC pin. This allows discontinuous conduction mode (DCM) operation down to near the limit defined by
Pulse-Skip Mode Operation
the chip’s minimum on-time (about 175ns). Below this With the MODE/SYNC pin tied to a DC voltage above 2V, output current level, the converter will begin to skip cycles Burst Mode operation is disabled. The internal, 0.525V in order to maintain output regulation. Figures 3 and 4 show buffered I the light load switching waveforms for Burst Mode and TH burst clamp is removed, allowing the ITH pin to directly control the current comparator from no pulse-skip mode operation for the converter in Figure 1. load to full load. With no load, the ITH pin is driven below 0.30V, the power MOSFET is turned off and sleep mode
Burst Mode Operation
is invoked. Oscilloscope waveforms illustrating this mode Burst Mode operation is selected by leaving the MODE/ of operation are shown in Figure 4. SYNC pin unconnected or by connecting it to ground. In When an external clock signal drives the MODE/SYNC normal operation, the range on the ITH pin corresponding to pin at a rate faster than the chip’s internal oscillator, the no load to full load is 0.30V to 1.2V. In Burst Mode opera- oscillator will synchronize to it. In this synchronized mode, tion, if the error amplifier EA drives the ITH voltage below Burst Mode operation is disabled. The constant frequency 0.525V, the buffered ITH input to the current comparator associated with synchronized operation provides a more C1 will be clamped at 0.525V (which corresponds to 25% controlled noise spectrum from the converter, at the ex- of maximum load current). The inductor current peak is pense of overall system efficiency of light loads. then held at approximately 30mV divided by the power MOSFET RDS(ON). If the ITH pin drops below 0.30V, the When the oscillator’s internal logic circuitry detects a Burst Mode comparator B1 will turn off the power MOSFET synchronizing signal on the MODE/SYNC pin, the in- and scale back the quiescent current of the IC to 250µA ternal oscillator ramp is terminated early and the slope (sleep mode). In this condition, the load current will be compensation is increased by approximately 30%. As supplied by the output capacitor until the ITH voltage rises a result, in applications requiring synchronization, it is above the 50mV hysteresis of the burst comparator. At recommended that the nominal operating frequency of light loads, short bursts of switching (where the average the IC be programmed to be about 75% of the external clock frequency. Attempting to synchronize to too high an MODE/SYNC = 0V MODE/SYNC = INTVCC (Burst Mode OPERATION) (PULSE SKIP MODE) VOUT 50mV/DIV VOUT 50mV/DIV IL 5A/DIV IL 5A/DIV 10µs/DIV 18717 F03 2µs/DIV 18717 F04
Figure 3. LTC1871-7 Burst Mode Operation Figure 4. LTC1871-7 Low Output Current Operation with (MODE/SYNC = 0V) at Low Output Current Burst Mode Operation Disabled (MODE/SYNC = INTVCC)
18717fd 9 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Typical Application Related Parts