Datasheet LT3750 (Analog Devices) - 9

LT3750
U U W U APPLICATIO S I FOR ATIO
output capacitor is almost completely charged and is can result in improper operation. This most often mani- given by: fests itself in two ways. The first is when the primary wind- ing current looks distorted instead of triangular. This I • V substantially reduces the efficiency and increases the I PK TRANS = AVG D , 2 V ( + N • V ) charge time. The second way is when the LT3750 fails to OUT PK ( ) TRANS detect discontinuous mode after the first switching cycle. The output diode’s continuous forward current rating Both of these problems are solved by increasing the amount must exceed I of capacitive bypassing for the transformer. Choose ca- AVG,D. pacitors that can handle the high RMS ripple currents At a minimum, the diode must satisfy all the previously common in flyback regulators. mentioned specifications to guarantee proper operation. However, to optimize charge time, reverse recovery time
Output Capacitor Selection
and reverse bias leakage current should be considered. Excessive diode reverse recovery times can cause appre- For photoflash applications, the output capacitor will be ciable discharging of the output capacitor thereby in- discharged into a Xenon flash bulb. Only a pulse capacitor creasing charge time. Choose a diode with a reverse or photoflash capacitor is able to survive such a harsh recovery time of less than 100ns. Diode leakage current event. Igniting a typical Xenon bulb requires approxi- under high reverse bias bleeds the output capacitor of mately 250V to 350V stored on a capacitor on the order of charge, also increasing charge time. Choose a diode that hundreds of microfarads. has minimal reverse bias leakage current. Table 2 recom-
Table 3. Recommended Output Capacitor Vendors
mends several output diodes for various output voltages
VENDOR WEBSITE
with adequate reverse recovery time. Rubycon www.rubycon.com Cornell Dubilier www.cornell-dubilier.com
Table 2. Recommended Output Diodes
NWL www.nwl.com
PEAK REPETITIVE REVERSE NMOS Selection PART IDC VOLTAGE MANUFACTURER NUMBER (A) (V) PACKAGE
Choose an external NMOS with minimal gate charge and Diodes Inc. MURS140 1 400 SMB on resistance that satisfies current limit and voltage break- (www.diodes.com) MURS160 1 600 SMB down requirements. The gate is nominally driven to VCC – ES2G 2 400 SMB 2V during each charge cycle. Ensure that this does not US1M 1 1000 SMA exceed the maximum gate to source voltage rating of the Philips BYD147 1 400 SOD87 (www.semiconductors. BYD167 1 500 SOD87 NMOS but enhaces the channel enough to minimize the on philips.com) resistance. Similarly, the maximum drain-source voltage rating of the NMOS must exceed VTRANS + VOUT/N or the
Bypass Capacitor Selection
magnitude of the leakage inductance spike, whichever is greater. The maximum instantaneous drain current must Use a high quality X5R or X7R dielectric ceramic capacitor exceed current limit. Because the switching period de- placed close to the LT3750 to locally bypass the VCC and creases with output voltage, the average current through VTRANS pins. For most applications, a 1µF to 10µF ceramic the NMOS is greatest when the output is nearly charged capacitor should suffice for VCC and a 1µF to 10µF for the and is given by: VTRANS pin. The high peak currents flowing through the transformer I • V PK OUT PK ( ) I = necessitate a larger (>>10µF) capacitor to bypass the pri- AVG M , 2 V mary winding of the transformer. Inadequate bypassing ( + N • V ) OUT PK ( ) TRANS 3750fa 9