Datasheet LT3750 (Analog Devices) - 7

LT3750
U OPERATIO
a rate (VTRANS – VDS(ON))/LPRI. The input voltage is mir- voltage is reached, the VOUT comparator resets the master rored on the secondary winding –N • (VTRANS – VDS(ON)) latch and the DONE pin goes low. Otherwise, the device which reverse biases the diode and prevents current flow enters the next phase of operation. in the secondary winding. Thus, energy is stored in the core of the transformer.
4. Discontinuous Mode Detection
Once all the current is transferred to the output capacitor,
3. Secondary Energy Transfer
(VOUT + VDIODE)/N will appear across the primary winding. When current limit is reached, the current limit compara- A transformer with no energy cannot support a DC voltage, tor resets the NMOS on-latch and the device enters the so, the voltage across the primary will decay to zero. In third phase of operation, secondary energy transfer. The other words, the drain of the NMOS will ring down from energy stored in the transformer core forward biases the VTRANS + (VOUT + VDIODE)/N to VTRANS. When the drain diode and current flows into the output capacitor. During voltage falls to VTRANS + 36mV, the DCM comparator sets this time, the output voltage (neglecting the diode drop) is the NMOS on-latch and a new charge cycle begins. Steps reflected back to the primary coil. If the target output 2-4 continue until the target output voltage is reached. 3750fa 7