Datasheet LT3825 (Analog Devices) - 7

LT3825
PIN FUNCTIONS VC (Pin 9):
Pin used for frequency compensation for connects to the ground side. At maximum current (VC at the switcher control loop. It is the output of the feed- its maximum voltage) it has a 98mV threshold. The signal back amplifier and the input to the current comparator. is blanked (ignored) during the minimum turn-on time. Switcher frequency compensation components are normally placed on this pin to ground. The voltage on
CCMP (Pin 13):
Pin for external filter capacitor for the this pin is proportional to the peak primary switch cur- optional load compensation function. Load compensation rent. The feedback amplifier output is enabled during the reduces the effects of parasitic resistances in the feedback synchronous switch-on time. sensing path. A 0.1µF ceramic capacitor suffices for most applications. Short this pin to GND in less demanding ap-
UVLO (Pin 10):
A resistive divider from VIN to this pin sets plications that don’t require load compensation. an undervoltage lockout based upon VIN level (not VCC). When the UVLO pin is below its threshold, the gate drives
RCMP (Pin 14):
Pin for optional external load compensation are disabled, but the part draws its normal quiescent current resistor. Use of this pin allows for nominal compensation from V of parasitic resistances in the feedback sensing path. In CC. The VCC undervoltage lockout supersedes this function so V less demanding applications, this resistor is not needed CC must be great enough to start the part. and this pin can be left open. See Applications Informa- The bias current on this pin has hysteresis such that the tion for details. bias current is sourced when the UVLO threshold is ex- ceeded. This introduces a hysteresis at the pin equivalent
PGDLY (Pin 15):
Pin for external programming resistor to to the bias current change times the impedance of the set delay from synchronous gate turn-off to primary gate upper divider resistor. The user can control the amount turn-on. See Applications Information for details. of hysteresis by adjusting the impedance of the divider.
PG (Pin 16):
Gate Drive Pin for the Primary-Side MOS- See the Applications Information for details. Tie the UVLO FET Switch. Large dynamic currents flow during voltage pin to VCC if you are not using this function. transitions. See the Applications Information for details.
SENSE– (Pin 11), SENSE+ (Pin 12):
These pins are used
GND (Exposed Pad Pin 17):
This is the ground connec- to measure primary-side switch current through an ex- tion for both signal ground and gate driver grounds. This ternal sense resistor. Peak primary-side current is used GND must be connected to the PCB ground plane. Careful in the converter control loop. Make Kelvin connections attention must be paid to ground layout. See Applications to the sense resistor to reduce noise problems. SENSE– Information for details. 3825fe 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Revision History Related Parts