Datasheet LT3837 (Analog Devices) - 7

HerstellerAnalog Devices
BeschreibungIsolated No-Opto Synchronous Flyback Controller
Seiten / Seite28 / 7 — PIN FUNCTIONS. VC (Pin 9):. CCMP (Pin 13):. CMP (Pin 14):. UVLO (Pin …
Dateiformat / GrößePDF / 324 Kb
DokumentenspracheEnglisch

PIN FUNCTIONS. VC (Pin 9):. CCMP (Pin 13):. CMP (Pin 14):. UVLO (Pin 10):. PGDLY (Pin 15):. PG (Pin 16):. GND (Exposed Pad Pin 17):

PIN FUNCTIONS VC (Pin 9): CCMP (Pin 13): CMP (Pin 14): UVLO (Pin 10): PGDLY (Pin 15): PG (Pin 16): GND (Exposed Pad Pin 17):

Modelllinie für dieses Datenblatt

Textversion des Dokuments

LT3837
PIN FUNCTIONS VC (Pin 9):
Pin used for frequency compensation for the
CCMP (Pin 13):
Pin for external filter capacitor for the switcher control loop. It is the output of the feedback optional load compensation function. Load compensation amplifier and the input to the current comparator. Switcher reduces the effects of parasitic resistances in the feedback frequency compensation components are normally placed sensing path. A 0.1µF ceramic capacitor suffices for most on this pin to ground. The voltage on this pin is propor- applications. Short this pin to GND in less demanding ap- tional to the peak primary switch current. The feedback plications that don’t require load compensation. amplifier output is enabled during the synchronous switch
R
on time.
CMP (Pin 14):
Pin for optional external load compensation resistor. Use of this pin allows for nominal compensation
UVLO (Pin 10):
A resistive divider from VIN to this pin sets of parasitic resistances in the feedback sensing path. In an undervoltage lockout based upon VIN level (not VCC). less demanding applications, this resistor is not needed When the UVLO pin is below its threshold, the gate drives and this pin can be left open. See the Applications Infor- are disabled, but the part draws its normal quiescent current mation section for details. from VCC. The VCC undervoltage lockout supersedes this
PGDLY (Pin 15):
Pin for external programming resistor function so VCC must be great enough to start the part. to set delay from synchronous gate turn-off to primary The bias current on this pin has hysteresis such that the gate turn-on. See the Applications Information section bias current is sourced when the UVLO threshold is ex- for details. ceeded. This introduces a hysteresis at the pin equivalent
PG (Pin 16):
Gate drive pin for the primary side MOSFET to the bias current change times the impedance of the Switch. Large dynamic currents flow during voltage upper divider resistor. The user can control the amount transitions. See the Applications Information section for of hysteresis by adjusting the impedance of the divider. details. See the Applications Information section for details. Tie the UVLO pin to VCC if you are not using this function.
GND (Exposed Pad Pin 17):
This is the ground connec- tion for both signal ground and gate driver grounds. This
SENSE– (Pin 11), SENSE+ (Pin 12):
These pins are used to GND should be connected to the PCB ground plane for measure primary side switch current through an external electrical contact and rated thermal performance. Careful sense resistor. Peak primary side current is used in the attention must be paid to ground layout. See the Applica- converter control loop. Make Kelvin connections to the tions Information section for details. sense resistor to reduce noise problems. SENSE– con- nects to the ground side. At maximum current (VC at its maximum voltage) it has a 98mV threshold. The signal is blanked (ignored) during the minimum turn-on time. 3837fd 7 Document Outline features applications description Typical Application absolute maximum ratings Pin Configuration order information electrical characteristics typical performance characteristics pin functions block diagram flyback feedback amplifier timing diagram operation applications information typical application Package description Revision History related parts