Datasheet LTC3873-5 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | No RSENSE Constant Frequency Current Mode Boost/Flyback/SEPIC DC/DC Controller |
| Seiten / Seite | 16 / 8 — OPERATION. Current Sense. Soft-Start. Light Load Operation. Figure 4. … |
| Dateiformat / Größe | PDF / 180 Kb |
| Dokumentensprache | Englisch |
OPERATION. Current Sense. Soft-Start. Light Load Operation. Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
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LTC3873-5
OPERATION
VTURNON (nominally 4.1V) at least momentarily to enable (even at zero load current) and the regulator will start to LTC3873-5 operation. The VCC voltage is then allowed to fall skip cycles in order to maintain regulation. This behavior to VTURNOFF (nominally 2.9V) before undervoltage lockout allows the regulator to maintain constant frequency down disables the LTC3873-5. The RUN/SS pin can be driven to very light loads, resulting in low output ripple as well below VSHDN (nominally 0.7V) to force the LTC3873-5 into as low audible noise and reduced RF interference while shutdown. When the chip is off, the input supply current is providing high light load effi ciency. typically only 50μA. Keep in mind that VCC should exceed the gate threshold voltage of the switching MOSFET for
Current Sense
safe operation. During the switch on-time, the control circuit limits the maximum voltage drop across the current sense com-
Soft-Start
ponent to about 295mV, 110mV and 185mV at low duty Leave the RUN/SS pin open to use the internal 3.3ms cycle with IPRG tied to VIN, GND or left fl oating respec- soft-start. During the internal soft-start, a voltage ramp tively. It is reduced with increasing duty cycle as shown limits the VITH. 3.3ms is required for ITH to ramp from in Figure 4. zero current level to full current level. The soft-start can 300 be lengthened by placing an external capacitor from the RUN/SS pin to the GND. A 3μA current will charge the 250 IPRG = HIGH capacitor, pulling the RUN/SS pin above the shutdown TAGE (mV) threshold and a 15μA pull-up current will continue to ramp 200 IPRG = FLOAT RUN/SS to limit VITH during the start-up. When RUN/SS 150 is driven by an external logic, a minimum of 2.75V logic IPRG = LOW is recommended to allow the maximum I 100 TH range. 50
Light Load Operation
MAXIMUM CURRENT SENSE VOL Under very light load current conditions, the I 0 TH pin voltage 1 20 40 60 80 100 will be very close to 0.85V. As the load current decreases DUTY CYCLE (%) further, an internal offset at the current comparator input 3873-5 F04 will assure that the current comparator remains tripped
Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
38735fb 8
OPERATION
VTURNON (nominally 4.1V) at least momentarily to enable (even at zero load current) and the regulator will start to LTC3873-5 operation. The VCC voltage is then allowed to fall skip cycles in order to maintain regulation. This behavior to VTURNOFF (nominally 2.9V) before undervoltage lockout allows the regulator to maintain constant frequency down disables the LTC3873-5. The RUN/SS pin can be driven to very light loads, resulting in low output ripple as well below VSHDN (nominally 0.7V) to force the LTC3873-5 into as low audible noise and reduced RF interference while shutdown. When the chip is off, the input supply current is providing high light load effi ciency. typically only 50μA. Keep in mind that VCC should exceed the gate threshold voltage of the switching MOSFET for
Current Sense
safe operation. During the switch on-time, the control circuit limits the maximum voltage drop across the current sense com-
Soft-Start
ponent to about 295mV, 110mV and 185mV at low duty Leave the RUN/SS pin open to use the internal 3.3ms cycle with IPRG tied to VIN, GND or left fl oating respec- soft-start. During the internal soft-start, a voltage ramp tively. It is reduced with increasing duty cycle as shown limits the VITH. 3.3ms is required for ITH to ramp from in Figure 4. zero current level to full current level. The soft-start can 300 be lengthened by placing an external capacitor from the RUN/SS pin to the GND. A 3μA current will charge the 250 IPRG = HIGH capacitor, pulling the RUN/SS pin above the shutdown TAGE (mV) threshold and a 15μA pull-up current will continue to ramp 200 IPRG = FLOAT RUN/SS to limit VITH during the start-up. When RUN/SS 150 is driven by an external logic, a minimum of 2.75V logic IPRG = LOW is recommended to allow the maximum I 100 TH range. 50
Light Load Operation
MAXIMUM CURRENT SENSE VOL Under very light load current conditions, the I 0 TH pin voltage 1 20 40 60 80 100 will be very close to 0.85V. As the load current decreases DUTY CYCLE (%) further, an internal offset at the current comparator input 3873-5 F04 will assure that the current comparator remains tripped
Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
38735fb 8