Datasheet LTC3766 (Analog Devices) - 8

LTC3766
PIN FUNCTIONS (SSOP/QFN) SG (Pin 1/Pin 26):
Gate Drive for the Synchronous MOSFET.
V + – SOUT, VS , VS (Pins 11, 12, 13/Pins 8, 9, 10):
VSOUT is
FG (Pin 2/Pin 27):
Gate Drive for the Forward MOSFET. the output of a precision, unity-gain differential amplifier. Tie V + – S and VS to the output of the main DC/DC converter to
VSEC (Pin 3/Pin 28):
Volt-Second Limit. Connect a resistor achieve true remote differential sensing. Also, V + S is used from SW to VSEC, and a capacitor from VSEC to GND to set for directly sensing the output voltage for inductor ripple the maximum volt-second product that is applied to the cancellation. Do not exceed the output sourcing current main power transformer. The PWM on-time is terminated specification on the VSOUT pin or a fault will be generated. when the VSEC voltage exceeds the internally generated See the Applications Information section for details. threshold. Tie to GND if not used.
GND (Pin 14/Pin 11, Exposed Pad Pin 29):
Signal Ground
MODE (Pin 4/Pin 1):
For normal isolated applications and Kelvin Sense for SG Reverse Overcurrent. Connect to using the LTC3765, tie to either GND or VCC to set the power ground at the source of the synchronous MOSFET. operating voltage to either low voltage or high voltage The exposed pad must be soldered to PCB ground for modes respectively, as needed to drive the gates of the rated thermal performance. synchronous and forward MOSFETs. For nonisolated applications, tie to ground through either a 100k or 50k
FS/SYNC (Pin 15/Pin 12):
Combination Frequency Set and resistor to activate standalone mode (for low voltage or Sync Pin. Tie to VCC to run at 275kHz. Place a resistor to high voltage operation respectively). In this mode, the PT+ ground at this pin to set the frequency between 75kHz and pin may be directly connected to the gate of a primary-side 500kHz. To synchronize, drive this pin with a clock signal MOSFET, and a reference clock signal is generated on the to achieve PLL synchronization from 100kHz to 500kHz. PT– pin. In standalone mode, the FGD pin is ignored and Sources 20μA of current. the associated delay is set adaptively.
REGSD (Pin 16/Pin 13):
Regulator Shutdown Timer. Place
PHASE (Pin 5/Pin 2):
Control Input to the Phase Selector. a capacitor to ground to limit the time allowed for the high This pin determines the phasing of the internal controller voltage linear regulator controller to operate. When the CLK relative to the synchronizing signal at the FS/SYNC pin. REGSD voltage exceeds 1.21V, the linear regulator is shut down. This pin sources 13μA of current when the linear
FB (Pin 6/Pin 3):
The Inverting Input of the Main Loop regulator is active. Error Amplifier. Tie to VCC or other voltage greater than
–
2.5V to enable slave mode in PolyPhase applications.
IS (Pin 17/Pin 14):
Negative Input to the Current Sense Circuit. Connect to the negative end of a low side current
ITH (Pin 7/Pin 4):
The Output of the Main Loop Error sense resistor. When using a current sense transformer, Amplifier. Place compensation components between the tie this pin to V + CC for single-ended sensing on IS with a ITH pin and GND. higher maximum trip level.
RUN (Pin 8/Pin 5):
Run Control Input. Holding this pin
I + S (Pin 18/Pin 15):
Positive Input to the Current Sense below 1.22V will shut down the IC and reset the soft-start Circuit. Connect to the positive end of a low side cur- and REGSD pins to 0V. rent sense resistor or to the output of a current sense
SS (Pin 9/Pin 6):
Soft-Start Inputs. A capacitor to ground transformer. sets the ramp time of the output voltage.
SGD (Pin 19/Pin 16):
Synchronous Gate Rising Edge Delay.
I
A resistor to GND sets the delay from primary gate turn-
PK (Pin 10/Pin 7):
Peak Current Limit Inductor Ripple Cancellation. This pin is used to adjust the peak current off (PT+ falling) to SG rising (and FG falling). This delay limit based on the amount of inductor current ripple, thereby is used to optimize the dead time between the turn-off of providing a constant average output current during current the primary-side MOSFET and the turn-on of SG. Tie SGD limit. Place a resistor to GND that is proportional to the main to GND to set this delay adaptively based on the falling output inductor. Leave this pin floating for constant peak edge of the SW pin voltage. See Setting the Gate Driver current limit. Minimize parasitic capacitance on this pin. Delays in the Applications Information section. 3766fc 8 For more information www.linear.com/LTC3766 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Timing Diagram Operation Applications Information Typical Applications Typical Applications Typical Applications Package Description Revision History Typical Application Related Parts