Datasheet AD5750, AD5750-1, AD5750-2 (Analog Devices) - 10
| Hersteller | Analog Devices |
| Beschreibung | Industrial Current/Voltage Output Driver with Programmable Ranges |
| Seiten / Seite | 36 / 10 — AD5750/AD5750-1/AD5750-2. Data Sheet. ABSOLUTE MAXIMUM RATINGS. Table 4. … |
| Revision | F |
| Dateiformat / Größe | PDF / 831 Kb |
| Dokumentensprache | Englisch |
AD5750/AD5750-1/AD5750-2. Data Sheet. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter. Rating. ESD CAUTION
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AD5750/AD5750-1/AD5750-2 Data Sheet ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress
Table 4.
rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute AVDD to GND −0.3 V to +30 V maximum rating conditions for extended periods may affect AVSS to GND +0.3 V to −28 V device reliability. AVDD to AVSS −0.3 V to +58 V DVCC to GND −0.3 V to +7 V VSENSE+ to GND AVSS to AVDD
ESD CAUTION
VSENSE− to GND ±5.0 V Digital Inputs to GND −0.3 V to DVCC + 0.3 V or +7 V (whichever is less) Digital Outputs to GND −0.3 V to DVCC + 0.3 V or +7 V (whichever is less) VREF to GND −0.3 V to +7 V VIN to GND −0.3 V to +7 V VOUT, IOUT to GND AV SS to AVDD Operating Temperature Range, −40°C to +105°C Industrial Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C 32-Lead LFCSP Package θJA Thermal Impedance1 42°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3 kV 1 Simulated data based on a JEDEC 2S2P board with thermal vias. Rev. F | Page 10 of 36 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Terminology Theory of Operation Software Mode Current Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of AD5750/AD5750-1/AD5750-2 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Status Bit Read Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) External Current Setting Resistor Programmable Overrange Modes Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide
AD5750/AD5750-1/AD5750-2 Data Sheet ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to Stresses above those listed under Absolute Maximum Ratings 100 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress
Table 4.
rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute AVDD to GND −0.3 V to +30 V maximum rating conditions for extended periods may affect AVSS to GND +0.3 V to −28 V device reliability. AVDD to AVSS −0.3 V to +58 V DVCC to GND −0.3 V to +7 V VSENSE+ to GND AVSS to AVDD
ESD CAUTION
VSENSE− to GND ±5.0 V Digital Inputs to GND −0.3 V to DVCC + 0.3 V or +7 V (whichever is less) Digital Outputs to GND −0.3 V to DVCC + 0.3 V or +7 V (whichever is less) VREF to GND −0.3 V to +7 V VIN to GND −0.3 V to +7 V VOUT, IOUT to GND AV SS to AVDD Operating Temperature Range, −40°C to +105°C Industrial Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 125°C 32-Lead LFCSP Package θJA Thermal Impedance1 42°C/W Lead Temperature JEDEC industry standard Soldering J-STD-020 ESD (Human Body Model) 3 kV 1 Simulated data based on a JEDEC 2S2P board with thermal vias. Rev. F | Page 10 of 36 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Terminology Theory of Operation Software Mode Current Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of AD5750/AD5750-1/AD5750-2 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Status Bit Read Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) External Current Setting Resistor Programmable Overrange Modes Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide