Datasheet AD5751 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Industrial I/V Output Driver, Single-Supply, 55 V Maximum Supply, Programmable Ranges |
| Seiten / Seite | 32 / 7 — Data Sheet. AD5751. TIMING CHARACTERISTICS. Table 3. Parameter1, 2. Limit … |
| Revision | D |
| Dateiformat / Größe | PDF / 631 Kb |
| Dokumentensprache | Englisch |
Data Sheet. AD5751. TIMING CHARACTERISTICS. Table 3. Parameter1, 2. Limit at TMIN, TMAX. Unit. Description. Timing Diagrams. SCLK. SYNC
Textversion des Dokuments
Data Sheet AD5751 TIMING CHARACTERISTICS
AVDD = 12 V (± 10%) to 55 V (maximum), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ (5 kΩ for 0 V to 40 V range), CL = 200 pF, IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter1, 2 Limit at TMIN, TMAX Unit Description
t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 5 ns min SYNC falling edge to SCLK falling edge setup time t5 10 ns min 16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC) t6 5 ns min Minimum SYNC high time (write mode) t7 5 ns min Data setup time t8 5 ns min Data hold time t9, t10 1.5 µs max CLEAR pulse low/high activation time t11 5 ns min Minimum SYNC high time (read mode) t 12 40 ns max SCLK rising edge to SDO valid (SDO CL = 15 pF) t 13 10 ns min RESET pulse low time 1 Guaranteed by characterization, but not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
Timing Diagrams t1 SCLK 1 2 16 t t 3 2 t6 t t 4 5 SYNC t8 t7 SDIN D15 D0 CLEAR t10 t9 VOUT RESET t
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07269- Figure 2. Write Mode Timing Diagram Rev. D | Page 7 of 32 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Current Output Terminology Theory of Operation Software Mode Currrent Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of the AD5751 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Readback Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) External Current Setting Resistor Programmable Overrange Modes Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide
AVDD = 12 V (± 10%) to 55 V (maximum), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ (5 kΩ for 0 V to 40 V range), CL = 200 pF, IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter1, 2 Limit at TMIN, TMAX Unit Description
t1 20 ns min SCLK cycle time t2 8 ns min SCLK high time t3 8 ns min SCLK low time t4 5 ns min SYNC falling edge to SCLK falling edge setup time t5 10 ns min 16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC) t6 5 ns min Minimum SYNC high time (write mode) t7 5 ns min Data setup time t8 5 ns min Data hold time t9, t10 1.5 µs max CLEAR pulse low/high activation time t11 5 ns min Minimum SYNC high time (read mode) t 12 40 ns max SCLK rising edge to SDO valid (SDO CL = 15 pF) t 13 10 ns min RESET pulse low time 1 Guaranteed by characterization, but not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
Timing Diagrams t1 SCLK 1 2 16 t t 3 2 t6 t t 4 5 SYNC t8 t7 SDIN D15 D0 CLEAR t10 t9 VOUT RESET t
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07269- Figure 2. Write Mode Timing Diagram Rev. D | Page 7 of 32 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Current Output Terminology Theory of Operation Software Mode Currrent Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of the AD5751 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Readback Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) External Current Setting Resistor Programmable Overrange Modes Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide