Datasheet AD5748 (Analog Devices) - 8

AD5748 Data Sheet Timing Diagrams t1 SCLK 1 2 16 t t 3 2 t6 t t 4 5 SYNC t8 t7 SDIN D15 D0 CLEAR t10 t9 VOUT RESET t
02 0
13
2- 92 08 Figure 2. Write Mode Timing Diagram
1 2 16 SCLK SYNC t11 SDIN A2 A1 A0 R = 1 0 X X X X X X X X X X X t12 PEC OVER IOUT VOUT SDO X X X X X R3 R2 R1 R0 CLRSEL OUTEN RSET
03
ERROR TEMP FAULT FAULT
-0 22 89 0 Figure 3. Readback Mode Timing Diagram Rev. B | Page 8 of 32 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Terminology Theory of Operation Software Mode Current Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of the AD5748 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Readback Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) Current Setting Resistor Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide