LT1070 Design Manual (Linear Technology) - 10

Application Note 19 An internal 30Ω resistor and 5.6V Zener protect the 2.3V feedback pin from overvoltage stress. Maximum transient 30μA S1 Q55 TO voltage is ±15V. This high transient condition most com- SHUTDOWN Q56 CIRCUIT monly occurs during fast fall time output shorts if a FROM FLYBACK feedforward capacitor is used around the feedback di- AMPLIFIER FB 1.244V Q57 Q58 Q62 Q18 S2 vider. If a feedforward capacitor is used for DC output PIN V voltages greater than 15V, a resistor equal to V R21 C OUT/20mA 3k PIN should be used between the divider node and the feedback Q45 pin as shown in Figure 5. 60μA Q60 Q61 Q32 Q24 Keep in mind when using the LT1070 that the feedback pin reference voltage is referred to the ground pin of the S3 regulator, and the ground pin can have switch currents AN19 F06 exceeding 5A. Any resistance in the ground pin connection will degrade load regulation. Best regulation is obtained by
Figure 6. Error Amplifier
tying the grounded end of the feedback divider directly to the ground pin of the LT1070, as a separate connection from the power ground. This limits output voltage errors R21 and Q62. The 60μA tail current of the input transistors to just the drop across the ground pin resistance instead sets the gm of the error amplifier at 4400μmhos. Voltage of multiplying it by the feedback divider ratio. See discus- gain with no load is limited by transistor output impedance sion of ground pin. at ≈800. Maximum source and sink current is ≈220μA. The voltage on the VC pin determines the current level at which the output switch will turn off. For VC voltage below VOUT 0.9V (at 25°C), the output switch will be totally off (duty V C OUT *R = cycle = 0). Above 0.9V, the switch will turn on at each TO LT1070 20mA FEEDFORWARD CAPACITOR oscillator cycle, then turn off when switch current reaches FEEDBACK PIN USED FOR IMPROVED LOOP TRANSIENT RESPONSE a trip level set by V 1.24k OR SOFT START C voltage. This trip level is zero at VC = 0.9V, and increases to about 9A when VC reaches its *REQUIRED FOR VOUT > 15V AN19 F05 upper clamp level of 2V. These numbers are based on a duty cycle of 10%. Above 10%, switch turn-off is a function of both switch current and time. The time depen-
Figure 5
dence is caused by a small ramp fed into the current amplifier input. This ramp starts at ≈ 40% duty cycle, and is the source of the bend in the V
Compensation Pin (V
C vs duty cycle graph
C)
shown in Figure 7. This ramp is used to prevent a phenom- The VC pin is used for frequency compensation, current enon peculiar to “current mode” switching regulators limiting, soft start and shutdown. It is the output of the known as subharmonic oscillation. See section on error amplifier and the input of the current comparator. Subharmonic Oscillations for further details. The error amplifier circuit is shown in Figure 6. A second amplifier output is also tied to the VC pin. This Q57 and Q58 form a differential input stage whose collec- “flyback mode” amplifier is turned on only when current is tor currents are inverted and multiplied times four by Q55 drawn out of the feedback pin. This condition occurs and Q56. Q55 current is further inverted by Q60 and Q61 during start-up in the normal mode until the feedback to generate a current fed balanced output which can swing divider has raised the voltage at the feedback pin above from the 2.3V rail down to a clamp level of ≈0.4V as set by 0.45V. an19fc AN19-10