Minimizing Switching Regulator Residue in Linear Regulator Outputs (Linear Technology) - 5
| Autoren | Jim Williams |
| Hersteller | Linear Technology |
| Beschreibung | Application Note 101. Linear regulators are commonly employed to post-regulate switching regulator outputs. Benefits include improved stability, accuracy, transient response and lowered output impedance. Ideally, these performance gains would be accompanied by markedly reduced switching regulator generated ripple and spikes. In practice, all linear regulators encounter some difficulty with ripple and spikes, particularly as frequency rises. This publication explains the causes of linear regulators' dynamic limitations and presents board level techniques for improving ripple and spike rejection. A hardware based ripple/spike simulator is presented, enabling rapid breadboard testing under various conditions. Three appendices review ferrite beads, inductor based filters and probing practice for wideband, sub-millivolt signals. |
| Seiten / Seite | 12 / 5 — Ripple/Spike Simulator. Figure 6. Switching Regulator Output Simulator … |
| Dateiformat / Größe | PDF / 358 Kb |
| Dokumentensprache | Englisch |
Ripple/Spike Simulator. Figure 6. Switching Regulator Output Simulator Waveforms
Textversion des Dokuments
Application Note 101
Ripple/Spike Simulator
paths are combined at the linear regulator input. The func- Gaining understanding of the problem requires observing tion generator’s settable ramp output (trace A, Figure 6) regulator response to ripple and spikes under a variety of feeds the DC/ripple path made up of power amplifi er A1 conditions. It is desirable to be able to independently vary and associated components. A1 receives the ramp input ripple and spike parameters, including frequency, harmonic and DC bias information and drives the regulator under content, amplitude, duration and DC level. This is a very test. L1 and the 1Ω resistor allow A1 to drive the regula- versatile capability, permitting real time optimization and tor at ripple frequencies without instability. The wideband sensitivity analysis to various circuit variations. Although spike path is sourced from the function generator’s there is no substitute for observing linear regulator per- pulsed “sync” output (trace B). This output’s edges are formance under actual switching regulator driven condi- differentiated (trace C) and fed to bipolar comparator C1- tions, a hardware simulator makes surprises less likely. C2. The comparator outputs (traces D and E) are spikes Figure 5 provides this capability. It simulates a switching synchronized to the ramps infl ection points. Spike width regulator’s output with independantly settable DC, ripple is controlled by complementary DC threshold potentials and spike parameters. applied to C1 and C2 with the 1k potentiometer and A2. Diode gating and the paralleled logic inverters present A commercially available function generator combines with trace F to the spike amplitude control. Follower Q1 sums two parallel signal paths to form the circuit. DC and ripple the spikes with A1’s DC/ripple path, forming the linear are transmitted on a relatively slow path while wideband regulator’s input (trace G). spike information is processed via a fast path. The two A = 0.01V/DIV B = 5V/DIV C = 2V/DIV A = 0.2V/DIV D = 10V/DIV AC COUPLED ON 3.3VDC E = 10V/DIV B = 0.01V/DIV AC COUPLED ON 3VDC F = 10V/DIV G = 0.02V/DIV AC COUPLED- ON 3.3V 500ns/DIV DC 500ns/DIV
Figure 6. Switching Regulator Output Simulator Waveforms. Figure 7. Linear Regulator Input (Trace A) and Output (Trace Function Generator Supplies Ripple (Trace A) and Spike (Trace B) Ripple and Switching Spike Content for CIN = 1
μ
F, COUT = B) Path Information. Differentiated Spike Information's Bipolar 10
μ
F. Output Spikes, Driving 10
μ
F, Have Lower Amplitude, But Excursion (Trace C) is Compared by C1-C2, Resulting in Trace D Risetime Remains Fast and E Synchronized Spikes. Diode Gating/Inverters Present Trace F to Spike Amplitude Control. Q1 Sums Spikes with DC-Ripple Path From Power Amplifi er A1, Forming Linear Regulator Input (Trace G). Spike Width Set Abnormally Wide for Photographic Clarity
an101f AN101-5
Ripple/Spike Simulator
paths are combined at the linear regulator input. The func- Gaining understanding of the problem requires observing tion generator’s settable ramp output (trace A, Figure 6) regulator response to ripple and spikes under a variety of feeds the DC/ripple path made up of power amplifi er A1 conditions. It is desirable to be able to independently vary and associated components. A1 receives the ramp input ripple and spike parameters, including frequency, harmonic and DC bias information and drives the regulator under content, amplitude, duration and DC level. This is a very test. L1 and the 1Ω resistor allow A1 to drive the regula- versatile capability, permitting real time optimization and tor at ripple frequencies without instability. The wideband sensitivity analysis to various circuit variations. Although spike path is sourced from the function generator’s there is no substitute for observing linear regulator per- pulsed “sync” output (trace B). This output’s edges are formance under actual switching regulator driven condi- differentiated (trace C) and fed to bipolar comparator C1- tions, a hardware simulator makes surprises less likely. C2. The comparator outputs (traces D and E) are spikes Figure 5 provides this capability. It simulates a switching synchronized to the ramps infl ection points. Spike width regulator’s output with independantly settable DC, ripple is controlled by complementary DC threshold potentials and spike parameters. applied to C1 and C2 with the 1k potentiometer and A2. Diode gating and the paralleled logic inverters present A commercially available function generator combines with trace F to the spike amplitude control. Follower Q1 sums two parallel signal paths to form the circuit. DC and ripple the spikes with A1’s DC/ripple path, forming the linear are transmitted on a relatively slow path while wideband regulator’s input (trace G). spike information is processed via a fast path. The two A = 0.01V/DIV B = 5V/DIV C = 2V/DIV A = 0.2V/DIV D = 10V/DIV AC COUPLED ON 3.3VDC E = 10V/DIV B = 0.01V/DIV AC COUPLED ON 3VDC F = 10V/DIV G = 0.02V/DIV AC COUPLED- ON 3.3V 500ns/DIV DC 500ns/DIV
Figure 6. Switching Regulator Output Simulator Waveforms. Figure 7. Linear Regulator Input (Trace A) and Output (Trace Function Generator Supplies Ripple (Trace A) and Spike (Trace B) Ripple and Switching Spike Content for CIN = 1
μ
F, COUT = B) Path Information. Differentiated Spike Information's Bipolar 10
μ
F. Output Spikes, Driving 10
μ
F, Have Lower Amplitude, But Excursion (Trace C) is Compared by C1-C2, Resulting in Trace D Risetime Remains Fast and E Synchronized Spikes. Diode Gating/Inverters Present Trace F to Spike Amplitude Control. Q1 Sums Spikes with DC-Ripple Path From Power Amplifi er A1, Forming Linear Regulator Input (Trace G). Spike Width Set Abnormally Wide for Photographic Clarity
an101f AN101-5