Datasheet PIC16F18424, PIC16F18444, PIC16LF18424, PIC16LF18444 (Microchip) - 8

link to page 10
PIC16(L)F18424/44 Figure 4. 20-Pin UQFN (4x4)
Rev. 00-000020B 6/21/2016 T DA P ICS 4 5 D S 0/ D S RA RA V V RA 20 19 18 17 16 MCLR/VPP/RA3 1 15 RA1/ICSPCLK RC5 2 14 RA2 RC4 3 13 RC0 RC3 4 12 RC1 RC6 5 11 RC2 6 7 8 9 10 7 7 6 5 4 RC RB RB RB RB
Note: 
It is recommended that the exposed bottom pad be connected to VSS.
Related Links
20-Pin Allocation Table
Pin Allocation Tables 1 14/16-Pin Allocation Table I/O ADC NCO DAC DSM imers CCP CLC T PWM CWG MSSP ZCD CLKR Pull-up Basic Reference EUSART Interrupts 16-pin UQFN Comparator 14-pin PDIP/SOIC/TSSOP
ICDDAT RA0 13 12 ANA0 — C1IN0+ — DAC1OUT1 MDSRC
(1)
— — — — SS2
(1)
— — — — IOCA0 Y ICSPDAT C1IN0 ICDCLK RA1 12 11 ANA1 ADCVREF+ — DAC1VREF+ — — — — — — — — — — IOCA1 Y C2IN0- ICSPCLK CWG1IN
(1)
RA2 11 10 ANA2 ADCVREF- — — DAC1VREF- — T0CKI
(1)
CCP3IN
(1)
— — ZCD1 — — — IOCA2 Y INT
(1)
CWG2IN
(1)
MCLR RA3 4 3 — — — — — — T6IN
(1)
— — — — — — — — IOCA3 Y VPP CLKOUT T1G
(1)
RA4 3 2 ANA4 — — — — — — — — — — — — — IOCA4 Y SOSCO SMT1WIN
(1)
OSC2 T1CKI
(1)
CLKIN RA5 2 1 ANA5 — — — — — T2IN
(1)
— — — — — — CLCIN3
(1)
— IOCA5 Y SOSCI SMT1SIG
(1)
OSC1 © 2018 Microchip Technology Inc.
Datasheet Preliminary
DS40002000A-page 8 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Operation Modes eXtreme Low-Power (XLP) Features Digital Peripherals Analog Peripherals Flexible Oscillator Structure PIC16(L)F184XX Family Types Packages Pin Diagrams 1. 14/16-Pin Diagrams 2. 20-Pin Diagrams Pin Allocation Tables 1. 14/16-Pin Allocation Table 2. 20-Pin Allocation Table Table of Contents 1. Device Overview 1.1. New Core Features 1.1.1. XLP Technology 1.1.2. Multiple Oscillator Options and Features 1.2. Other Special Features 1.3. Details on Individual Family Members 1.4. Register and Bit naming conventions 1.4.1. Register Names 1.4.2. Bit Names 1.4.2.1. Short Bit Names 1.4.2.2. Long Bit Names 1.4.2.3. Bit Fields 1.4.3. Register and Bit Naming Exceptions 1.4.3.1. Status, Interrupt, and Mirror Bits 1.4.3.2. Legacy Peripherals 1.4.4. Register Legend 2. Guidelines for Getting Started with PIC16(L)F18424/44 Microcontrollers 2.1. Basic Connection Requirements 2.2. Power Supply Pins 2.2.1. Decoupling Capacitors 2.2.2. Tank Capacitors 2.3. Master Clear (MCLR) Pin 2.4. In-Circuit Serial Programming™ ICSP™ Pins 2.5. External Oscillator Pins 2.6. Unused I/Os 3. Enhanced Mid-Range CPU 3.1. Automatic Interrupt Context Saving 3.2. 16-Level Stack with Overflow and Underflow 3.3. File Select Registers 3.4. Instruction Set 4. Device Configuration 4.1. Configuration Words 4.2. Code Protection 4.2.1. Program Memory Protection 4.3. Write Protection 4.4. User ID 4.5. Device ID and Revision ID 4.6. Register Summary - Configuration Words 4.7. Register Definitions: Configuration Words 4.7.1. CONFIG1 4.7.2. CONFIG2 4.7.3. CONFIG3 4.7.4. CONFIG4 4.7.5. CONFIG5 4.8. Register Summary - Device and Revision 4.9. Register Definitions: Device and Revision 4.9.1. DEVICE ID 4.9.2. REVISION ID 5. Device Information Area 5.1. Microchip Unique identifier (MUI) 5.2. External Unique Identifier (EUI) 5.3. Analog-to-Digital Conversion Data of the Temperature Sensor 5.4. Fixed Voltage Reference Data 6. Device Configuration Information 6.1. DIA and DCI Access 7. Memory Organization 7.1. Program Memory Organization 7.1.1. Reading Program Memory as Data 7.1.1.1. RETLW Instruction 7.1.1.2. Indirect Read with FSR 7.2. Memory Access Partition (MAP) 7.2.1. Application Block 7.2.2. Boot Block 7.2.3. Storage Area Flash 7.2.4. Memory Write Protection 7.2.5. Memory Violation 7.3. Data Memory Organization 7.3.1. Bank Selection 7.3.2. Core Registers 7.3.2.1. STATUS Register 7.3.3. Special Function Register 7.3.4. General Purpose RAM 7.3.4.1. Linear Access to GPR 7.3.5. Common RAM 7.4. PCL and PCLATH 7.4.1. Modifying PCL 7.4.2. Computed GOTO 7.4.3. Computed Function Calls 7.4.4. Branching 7.5. Stack 7.5.1. Accessing the Stack 7.5.2. Overflow/Underflow Reset 7.6. Indirect Addressing 7.6.1. Traditional/Banked Data Memory 7.6.2. Linear Data Memory 7.6.3. Program Flash Memory 7.7. Register Summary - Memory and Status 7.8. Register Definitions: Memory and Status 7.8.1. INDF0 7.8.2. INDF1 7.8.3. PCL 7.8.4. STATUS 7.8.5. FSR0 7.8.6. FSR1 7.8.7. BSR 7.8.8. WREG 7.8.9. PCLATH 7.8.10. INTCON 7.8.11. TOS 7.8.12. STKPTR 7.9. Register Summary: Shadow Registers 7.10. Register Definitions: Shadow Registers 7.10.1. STATUS_SHAD 7.10.2. WREG_SHAD 7.10.3. BSR_SHAD 7.10.4. PCLATH_SHAD 7.10.5. FSR_SHAD 8. Resets 8.1. Power-on Reset (POR) 8.2. Brown-out Reset (BOR) 8.2.1. BOR is Always On 8.2.2. BOR is OFF in Sleep 8.2.3. BOR Controlled by Software 8.2.4. BOR is Always Off 8.3. Low-Power Brown-out Reset (LPBOR) 8.3.1. Enabling LPBOR 8.3.2. LPBOR Module Output 8.4. MCLR 8.4.1. MCLR Enabled 8.4.2. MCLR Disabled 8.5. Windowed Watchdog Timer (WWDT) Reset 8.6. RESET Instruction 8.7. Stack Overflow/Underflow Reset 8.8. Programming Mode Exit 8.9. Power-up Timer (PWRT) 8.10. Start-up Sequence 8.11. Memory Execution Violation 8.12. Determining the Cause of a Reset 8.13. Power Control (PCONx) Register 8.14. Register Summary - BOR Control and Power Control 8.15. Register Definitions: Power Control 8.15.1. BORCON 8.15.2. PCON0 8.15.3. PCON1 9. Oscillator Module (with Fail-Safe Clock Monitor) 9.1. Overview 9.2. Clock Source Types 9.2.1. External Clock Sources 9.2.1.1. EC Mode 9.2.1.2. LP, XT, HS Modes 9.2.1.3. Oscillator Start-up Timer (OST) 9.2.1.4. 4x PLL 9.2.1.5. Secondary Oscillator 9.2.2. Internal Clock Sources 9.2.2.1. HFINTOSC 9.2.2.2. MFINTOSC 9.2.2.3. 2x PLL 9.2.2.4. Internal Oscillator Frequency Adjustment 9.2.2.5. LFINTOSC 9.2.2.6. ADCRC (also referred to as FRC) 9.2.2.7. Oscillator Status and Manual Enable 9.2.2.8. HFOR and MFOR Bits 9.3. Clock Switching 9.3.1. New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) Bits 9.3.2. PLL Input Switch 9.3.3. Clock Switch and Sleep 9.4. Fail-Safe Clock Monitor 9.4.1. Fail-Safe Detection 9.4.2. Fail-Safe Operation 9.4.3. Fail-Safe Condition Clearing 9.4.4. Reset or Wake-up from Sleep 9.5. Register Summary - OSC 9.6. Register Definitions: Oscillator Control 9.6.1. OSCCON1 9.6.2. OSCCON2 9.6.3. OSCCON3 9.6.4. OSCSTAT 9.6.5. OSCEN 9.6.6. OSCTUNE 9.6.7. OSCFRQ 10. Interrupts 10.1. Operation 10.2. Interrupt Latency 10.3. Interrupts During Sleep 10.4. INT Pin 10.5. Automatic Context Saving 10.6. Register Summary - Interrupt Control 10.7. Register Definitions: Interrupt Control 10.7.1. INTCON 10.7.2. PIE0 10.7.3. PIE1 10.7.4. PIE2 10.7.5. PIE3 10.7.6. PIE4 10.7.7. PIE5 10.7.8. PIE6 10.7.9. PIE7 10.7.10. PIE8 10.7.11. PIR0 10.7.12. PIR1 10.7.13. PIR2 10.7.14. PIR3 10.7.15. PIR4 10.7.16. PIR5 10.7.17. PIR6 10.7.18. PIR7 10.7.19. PIR8 11. Power-Saving Operation Modes 11.1. Doze Mode 11.1.1. Doze Operation 11.1.2. Interrupts During Doze 11.2. Sleep Mode 11.2.1. Wake-up from Sleep 11.2.2. Wake-up Using Interrupts 11.2.3. Low-Power Sleep Mode 11.2.3.1. Sleep Current vs. Wake-up Time 11.2.3.2. Peripheral Usage in Sleep 11.3. Idle Mode 11.3.1. Idle and Interrupts 11.3.2. Idle and WWDT 11.4. Register Summary - Power Savings Control 11.5. Register Definitions: Power Savings Control 11.5.1. VREGCON 11.5.2. CPUDOZE 12. (WWDT) Windowed Watchdog Timer 12.1. Independent Clock Source 12.2. WWDT Operating Modes 12.2.1. WWDT Is Always On 12.2.2. WWDT Is Off in Sleep 12.2.3. WWDT Controlled by Software 12.3. Time-out Period 12.4. Watchdog Window 12.5. Clearing the WWDT 12.5.1. CLRWDT Considerations (Windowed Mode) 12.6. Operation During Sleep 12.7. Register Summary - WDT Control 12.8. Register Definitions: Windowed Watchdog Timer Control 12.8.1. WDTCON0 12.8.2. WDTCON1 12.8.3. WDTPSH 12.8.4. WDTPSL 12.8.5. WDTTMR 13. (NVM) Nonvolatile Memory Control 13.1. Program Flash Memory 13.1.1. Program Memory Voltages 13.1.1.1. Programming Externally 13.1.1.2. Self-programming 13.2. Data EEPROM 13.3. FSR and INDF Access 13.3.1. FSR Read 13.3.2. FSR Write 13.4. NVMREG Access 13.4.1. NVMREG Read Operation 13.4.2. NVM Unlock Sequence 13.4.3. NVMREG Write to EEPROM 13.4.4. NVMREG Erase of Program Memory 13.4.5. NVMREG Write to Program Memory 13.4.6. Modifying Flash Program Memory 13.4.7. NVMREG Access to Device Information Area, Device Configuration Area, User ID, Device ID, EEPROM, and Configuration Words 13.4.8. Write Verify 13.4.9. WRERR Bit 13.5. Register Summary: NVM Control 13.6. Register Definitions: Nonvolatile Memory 13.6.1. NVMADR 13.6.2. NVMDAT 13.6.3. NVMCON1 13.6.4. NVMCON2 14. I/O Ports 14.1. PORT Availability 14.2. I/O Ports Description 14.3. I/O Priorities 14.4. PORTx Registers 14.4.1. Data Register 14.4.2. Direction Control 14.4.3. Open-Drain Control 14.4.4. Slew Rate Control 14.4.5. Input Threshold Control 14.4.6. Analog Control 14.4.7. Weak Pull-up Control 14.4.8. PORTx Functions and Output Priorities 14.5. Register Summary - Input/Output 14.6. Register Definitions: Port Control 14.6.1. PORTA 14.6.2. PORTB 14.6.3. PORTC 14.6.4. TRISA 14.6.5. TRISB 14.6.6. TRISC 14.6.7. LATA 14.6.8. LATB 14.6.9. LATC 14.6.10. ANSELA 14.6.11. ANSELB 14.6.12. ANSELC 14.6.13. WPUA 14.6.14. WPUB 14.6.15. WPUC 14.6.16. ODCONA 14.6.17. ODCONB 14.6.18. ODCONC 14.6.19. SLRCONA 14.6.20. SLRCONB 14.6.21. SLRCONC 14.6.22. INLVLA 14.6.23. INLVLB 14.6.24. INLVLC 15. (PPS) Peripheral Pin Select Module 15.1. PPS Inputs 15.2. PPS Outputs 15.3. Bidirectional Pins 15.4. PPS Lock 15.5. PPS Permanent Lock 15.6. Operation During Sleep 15.7. Effects of a Reset 15.8. Register Summary - PPS 15.9. Register Definitions: PPS Input and Output Selection 15.9.1. Peripheral xxx Input Selection 15.9.2. Pin Rxy Output Source Selection Register 15.9.3. PPS Lock Register 16. (PMD) Peripheral Module Disable 16.1. Disabling a Module 16.2. Enabling a Module 16.3. System Clock Disable 16.4. Register Summary - PMD 16.5. Register Definitions: Peripheral Module Disable 16.5.1. PMD0 16.5.2. PMD1 16.5.3. PMD2 16.5.4. PMD3 16.5.5. PMD4 16.5.6. PMD5 16.5.7. PMD6 16.5.8. PMD7 17. Interrupt-on-Change 17.1. Enabling the Module 17.2. Individual Pin Configuration 17.3. Interrupt Flags 17.3.1. Clearing Interrupt Flags 17.4. Operation in Sleep 17.5. Register Summary - Interrupt-on-Change 17.6. Register Definitions: Interrupt-on-Change Control 17.6.1. IOCAP 17.6.2. IOCAN 17.6.3. IOCAF 17.6.4. IOCBP 17.6.5. IOCBN 17.6.6. IOCBF 17.6.7. IOCCP 17.6.8. IOCCN 17.6.9. IOCCF 18. (FVR) Fixed Voltage Reference 18.1. Independent Gain Amplifiers 18.2. FVR Stabilization Period 18.3. Register Summary - FVR 18.4. Register Definitions: FVR Control 18.4.1. FVRCON 19. Temperature Indicator Module 19.1. Module Operation 19.2. Minimum Operating VDD 19.3. Temperature Indicator Range 19.4. Estimation of Temperature 19.4.1. Calibration 19.4.1.1. Higher-Order Calibration 19.4.2. Temperature Resolution 19.5. ADC Acquisition Time 20. (ADC2) Analog-to-Digital Converter with Computation Module 20.1. ADC Configuration 20.1.1. Port Configuration 20.1.2. Channel Selection 20.1.3. ADC Voltage Reference 20.1.4. Conversion Clock 20.1.5. Interrupts 20.1.6. Result Formatting 20.2. ADC Operation 20.2.1. Starting a Conversion 20.2.2. Completion of a Conversion 20.2.3. Terminating a Conversion 20.2.4. ADC Operation During Sleep 20.2.5. External Trigger During Sleep 20.2.6. Auto-Conversion Trigger 20.2.7. ADC Conversion Procedure (Basic Mode) 20.3. ADC Acquisition Requirements 20.4. ADC Charge Pump 20.5. Capacitive Voltage Divider (CVD) Features 20.5.1. CVD Operation 20.5.2. Precharge Control 20.5.3. Acquisition Control for CVD 20.5.4. Guard Ring Outputs 20.5.5. Additional Sample and Hold Capacitance 20.6. Computation Operation 20.6.1. Digital Filter/Average 20.6.2. Basic Mode 20.6.3. Accumulate Mode 20.6.4. Average Mode 20.6.5. Burst Average Mode 20.6.6. Low-pass Filter Mode 20.6.7. Threshold Comparison 20.6.8. Continuous Sampling Mode 20.6.9. Double Sample Conversion 20.7. Register Summary - ADC Control 20.8. Register Definitions: ADC Control 20.8.1. ADCON0 20.8.2. ADCON1 20.8.3. ADCON2 20.8.4. ADCON3 20.8.5. ADSTAT 20.8.6. ADCLK 20.8.7. ADREF 20.8.8. ADPCH 20.8.9. ADPRE 20.8.10. ADACQ 20.8.11. ADCAP 20.8.12. ADRPT 20.8.13. ADCNT 20.8.14. ADFLTR 20.8.15. ADRES 20.8.16. ADPREV 20.8.17. ADACC 20.8.18. ADSTPT 20.8.19. ADERR 20.8.20. ADLTH 20.8.21. ADUTH 20.8.22. ADACT 20.8.23. ADCPCON0 21. (DAC) 5-Bit Digital-to-Analog Converter Module 21.1. Output Voltage Selection 21.2. Ratiometric Output Level 21.3. DAC Voltage Reference Output 21.4. Operation During Sleep 21.5. Effects of a Reset 21.6. Register Summary - DAC Control 21.7. Register Definitions: DAC Control 21.7.1. DAC1CON0 21.7.2. DAC1CON1 22. Numerically Controlled Oscillator (NCO) Module 22.1. NCO Operation 22.1.1. NCO Clock Sources 22.1.2. Accumulator 22.1.3. Adder 22.1.4. Increment Registers 22.2. Fixed Duty Cycle Mode 22.3. Pulse Frequency Mode 22.3.1. Output Pulse Width Control 22.4. Output Polarity Control 22.5. Interrupts 22.6. Effects of a Reset 22.7. Operation in Sleep 22.8. Register Summary - NCO 22.9. Register Definitions: NCO 22.9.1. NCOxCON 22.9.2. NCOxCLK 22.9.3. NCOxACC 22.9.4. NCOxINC 23. (CMP) Comparator Module 23.1. Comparator Overview 23.2. Comparator Control 23.2.1. Comparator Enable 23.2.2. Comparator Output 23.2.3. Comparator Output Polarity 23.3. Comparator Hysteresis 23.4. Operation With Timer1 Gate 23.4.1. Comparator Output Synchronization 23.5. Comparator Interrupt 23.6. Comparator Positive Input Selection 23.7. Comparator Negative Input Selection 23.8. Comparator Response Time 23.9. Analog Input Connection Considerations 23.10. CWG1 Auto-Shutdown Source 23.11. ADC Auto-Trigger Source 23.12. Even Numbered Timers Reset 23.13. Operation in Sleep Mode 23.14. Register Summary - Comparator 23.15. Register Definitions: Comparator Control 23.15.1. CMxCON0 23.15.2. CMxCON1 23.15.3. CMxNCH 23.15.4. CMxPCH 23.15.5. CMOUT 24. Timer0 Module 24.1. Timer0 Operation 24.1.1. 8-bit Mode 24.1.2. 16-Bit Mode 24.2. Clock Selection 24.2.1. Clock Source Selection 24.2.2. Synchronous Mode 24.2.3. Asynchronous Mode 24.2.4. Programmable Prescaler 24.3. Timer0 Output and Interrupt 24.3.1. Programmable Postscaler 24.3.2. Timer0 Output 24.3.3. Timer0 Interrupt 24.3.4. Timer0 Example 24.4. Operation During Sleep 24.5. Register Summary - Timer0 24.6. Register Definitions: Timer0 Control 24.6.1. T0CON0 24.6.2. T0CON1 24.6.3. TMR0H 24.6.4. TMR0L 25. Timer1 Module with Gate Control 25.1. Timer1 Operation 25.2. Clock Source Selection 25.2.1. Internal Clock Source 25.2.2. External Clock Source 25.3. Timer1 Prescaler 25.4. Secondary Oscillator 25.5. Timer1 Operation in Asynchronous Counter Mode 25.5.1. Reading and Writing Timer1 in Asynchronous Counter Mode 25.6. Timer1 16-Bit Read/Write Mode 25.7. Timer1 Gate 25.7.1. Timer1 Gate Enable 25.7.2. Timer1 Gate Source Selection 25.7.3. Timer1 Gate Toggle Mode 25.7.4. Timer1 Gate Single-Pulse Mode 25.7.5. Timer1 Gate Value Status 25.7.6. Timer1 Gate Event Interrupt 25.8. Timer1 Interrupt 25.9. Timer1 Operation During Sleep 25.10. CCP Capture/Compare Time Base 25.11. CCP Special Event Trigger 25.12. Peripheral Module Disable 25.13. Register Summary - Timer1 25.14. Register Definitions: Timer1 25.14.1. TxCON 25.14.2. TxGCON 25.14.3. TMRxCLK 25.14.4. TMRxGATE 25.14.5. TMRx 26. Timer2 Module 26.1. Timer2 Operation 26.1.1. Free Running Period Mode 26.1.2. One-Shot Mode 26.1.3. Monostable Mode 26.2. Timer2 Output 26.3. External Reset Sources 26.4. Timer2 Interrupt 26.5. Operating Modes 26.6. Operation Examples 26.6.1. Software Gate Mode 26.6.2. Hardware Gate Mode 26.6.3. Edge-Triggered Hardware Limit Mode 26.6.4. Level-Triggered Hardware Limit Mode 26.6.5. Software Start One-Shot Mode 26.6.6. Edge-Triggered One-Shot Mode 26.6.7. Edge-Triggered Hardware Limit One-Shot Mode 26.6.8. Level Reset, Edge-Triggered Hardware Limit One-Shot Modes 26.6.9. Edge-Triggered Monostable Modes 26.6.10. Level-Triggered Hardware Limit One-Shot Modes 26.7. Timer2 Operation During Sleep 26.8. Register Summary - Timer2 26.9. Register Definitions: Timer2 Control 26.9.1. TxTMR 26.9.2. TxPR 26.9.3. TxCON 26.9.4. TxHLT 26.9.5. TxCLKCON 26.9.6. TxRST 27. (ZCD) Zero-Cross Detection Module 27.1. External Resistor Selection 27.2. ZCD Logic Output 27.3. ZCD Logic Polarity 27.4. ZCD Interrupts 27.5. Correction for ZCPINV Offset 27.5.1. Correction by AC Coupling 27.5.2. Correction By Offset Current 27.6. Handling VPEAK Variations 27.7. Operation During Sleep 27.8. Effects of a Reset 27.9. Disabling the ZCD Module 27.10. Register Summary: ZCD Control 27.11. Register Definitions: ZCD Control 27.11.1. ZCDCON 28. CCP/PWM Timer Resource Selection 28.1. Register Summary - Timer Selection Registers for CCP/PWM 28.2. Register Definitions: CCP/PWM Timer Selection 28.2.1. CCPTMRS0 28.2.2. CCPTMRS1 29. Capture/Compare/PWM Module 29.1. CCP Module Configuration 29.1.1. CCP Modules and Timer Resources 29.1.2. Open-Drain Output Option 29.2. Capture Mode 29.2.1. Capture Sources 29.2.2. Timer1 Mode Resource 29.2.3. Software Interrupt Mode 29.2.4. CCP Prescaler 29.2.5. Capture During Sleep 29.3. Compare Mode 29.3.1. CCPx Pin Configuration 29.3.2. Timer1 Mode Resource 29.3.3. Auto-Conversion Trigger 29.3.4. Compare During Sleep 29.4. PWM Overview 29.4.1. Standard PWM Operation 29.4.2. Setup for PWM Operation 29.4.3. Timer2 Timer Resource 29.4.4. PWM Period 29.4.5. PWM Duty Cycle 29.4.6. PWM Resolution 29.4.7. Operation in Sleep Mode 29.4.8. Changes in System Clock Frequency 29.4.9. Effects of Reset 29.5. Register Summary - CCP Control 29.6. Register Definitions: CCP Control 29.6.1. CCPxCON 29.6.2. CCPxCAP 29.6.3. CCPRx 30. (PWM) Pulse-Width Modulation 30.1. Fundamental Operation 30.2. PWM Output Polarity 30.3. PWM Period 30.4. PWM Duty Cycle 30.5. PWM Resolution 30.6. Operation in Sleep Mode 30.7. Changes in System Clock Frequency 30.8. Effects of Reset 30.9. Setup for PWM Operation using PWMx Output Pins 30.9.1. PWMx Pin Configuration 30.10. Setup for PWM Operation to Other Device Peripherals 30.11. Register Summary - Registers Associated with PWM 30.12. Register Definitions: PWM Control 30.12.1. PWMxCON 30.12.2. PWMxDC 31. (CWG) Complementary Waveform Generator Module 31.1. Fundamental Operation 31.2. Operating Modes 31.2.1. Half-Bridge Mode 31.2.2. Push-Pull Mode 31.2.3. Full-Bridge Modes 31.2.3.1. Direction Change in Full-Bridge Mode 31.2.3.2. Dead-Band Delay in Full-Bridge Mode 31.2.4. Steering Modes 31.2.4.1. Synchronous Steering Mode 31.2.4.2. Asynchronous Steering Mode 31.3. Start-up Considerations 31.4. Clock Source 31.5. Selectable Input Sources 31.6. Output Control 31.6.1. CWG Outputs 31.6.2. Polarity Control 31.7. Dead-Band Control 31.7.1. Dead-Band Functionality in Half-Bridge mode 31.7.2. Dead-Band Functionality in Full-Bridge mode 31.8. Rising Edge and Reverse Dead Band 31.9. Falling Edge and Forward Dead Band 31.10. Dead-Band Jitter 31.11. Auto-Shutdown 31.11.1. Shutdown 31.11.1.1. Software Generated Shutdown 31.11.1.2. External Input Source 31.11.1.3. Pin Override Levels 31.11.1.4. Auto-Shutdown Interrupts 31.11.2. Auto-Shutdown Restart 31.11.2.1. Software-Controlled Restart 31.11.2.2. Auto-Restart 31.12. Operation During Sleep 31.13. Configuring the CWG 31.14. Register Summary - CWG Control 31.15. Register Definitions: CWG Control 31.15.1. CWGxCON0 31.15.2. CWGxCON1 31.15.3. CWGxCLK 31.15.4. CWGxISM 31.15.5. CWGxSTR 31.15.6. CWGxAS0 31.15.7. CWGxAS1 31.15.8. CWGxDBR 31.15.9. CWGxDBF 32. (DSM) Data Signal Modulator Module 32.1. DSM Operation 32.2. Modulator Signal Sources 32.3. Carrier Signal Sources 32.4. Carrier Synchronization 32.5. Carrier Source Polarity Select 32.6. Programmable Modulator Data 32.7. Modulated Output Polarity 32.8. Operation in Sleep Mode 32.9. Effects of a Reset 32.10. Peripheral Module Disable 32.11. Register Summary - DSM 32.12. Register Definitions: Modulation Control 32.12.1. MDxCON0 32.12.2. MDxCON1 32.12.3. MDxCARH 32.12.4. MDxCARL 32.12.5. MDxSRC 33. (CLC) Configurable Logic Cell 33.1. CLC Setup 33.1.1. Data Selection 33.1.2. Data Gating 33.1.3. Logic Function 33.1.4. Output Polarity 33.2. CLC Interrupts 33.3. Output Mirror Copies 33.4. Effects of a Reset 33.5. Operation During Sleep 33.6. CLC Setup Steps 33.7. Register Summary - CLC Control 33.8. Register Definitions: Configurable Logic Cell 33.8.1. CLCxCON 33.8.2. CLCxPOL 33.8.3. CLCxSEL0 33.8.4. CLCxSEL1 33.8.5. CLCxSEL2 33.8.6. CLCxSEL3 33.8.7. CLCxGLS0 33.8.8. CLCxGLS1 33.8.9. CLCxGLS2 33.8.10. CLCxGLS3 33.8.11. CLCDATA 34. Reference Clock Output Module 34.1. Clock Source 34.1.1. Clock Synchronization 34.2. Programmable Clock Divider 34.3. Selectable Duty Cycle 34.4. Operation in Sleep Mode 34.5. Register Summary: Reference CLK 34.6. Register Definitions: Reference Clock 34.6.1. CLKRCON 34.6.2. CLKRCLK 35. (MSSP) Master Synchronous Serial Port Module 35.1. SPI Mode Overview 35.1.1. SPI Mode Registers 35.2. SPI Mode Operation 35.2.1. SPI Master Mode 35.2.2. SPI Slave Mode 35.2.3. Daisy-Chain Configuration 35.2.4. Slave Select Synchronization 35.2.5. SPI Operation in Sleep Mode 35.3. I2C Mode Overview 35.3.1. Register Definitions: I2C Mode 35.4. I2C Mode Operation 35.4.1. Clock Stretching 35.4.2. Arbitration 35.4.3. Byte Format 35.4.4. Definition of I2C Terminology 35.4.5. SDA and SCL Pins 35.4.6. SDA Hold Time 35.4.7. Start Condition 35.4.8. Stop Condition 35.4.9. Restart Condition 35.4.10. Start/Stop Condition Interrupt Masking 35.4.11. Acknowledge Sequence 35.5. I2C Slave Mode Operation 35.5.1. Slave Mode Addresses 35.5.1.1. I2C Slave 7-bit Addressing Mode 35.5.1.2. I2C Slave 10-bit Addressing Mode 35.5.2. Slave Reception 35.5.2.1. 7-bit Addressing Reception 35.5.2.2. 7-bit Reception with AHEN and DHEN 35.5.3. Slave Transmission 35.5.3.1. Slave Mode Bus Collision 35.5.3.2. 7-bit Transmission 35.5.3.3. 7-bit Transmission with Address Hold Enabled 35.5.4. Slave Mode 10-bit Address Reception 35.5.5. 10-bit Addressing with Address or Data Hold 35.5.6. Clock Stretching 35.5.6.1. Normal Clock Stretching 35.5.6.2. 10-bit Addressing Mode 35.5.6.3. Byte NACKing 35.5.7. Clock Synchronization and the CKP bit 35.5.8. General Call Address Support 35.5.9. SSP Mask Register 35.6. I2C Master Mode 35.6.1. I2C Master Mode Operation 35.6.2. Clock Arbitration 35.6.3. WCOL Status Flag 35.6.4. I2C Master Mode Start Condition Timing 35.6.5. I2C Master Mode Repeated Start Condition Timing 35.6.6. I2C Master Mode Transmission 35.6.6.1. BF Status Flag 35.6.6.2. WCOL Status Flag 35.6.6.3. ACKSTAT Status Flag 35.6.6.4. Typical transmit sequence: 35.6.7. I2C Master Mode Reception 35.6.7.1. BF Status Flag 35.6.7.2. SSPOV Status Flag 35.6.7.3. WCOL Status Flag 35.6.7.4. Typical Receive Sequence: 35.6.8. Acknowledge Sequence Timing 35.6.8.1. Acknowledge Write Collision 35.6.9. Stop Condition Timing 35.6.9.1. Write Collision on Stop 35.6.10. Sleep Operation 35.6.11. Effects of a Reset 35.6.12. Multi-Master Mode 35.6.13. Multi -Master Communication, Bus Collision and Bus Arbitration 35.6.13.1. Bus Collision During a Start Condition 35.6.13.2. Bus Collision During a Repeated Start Condition 35.6.13.3. Bus Collision During a Stop Condition 35.7. Baud Rate Generator 35.8. Register Summary: MSSP Control 35.9. Register Definitions: MSSP Control 35.9.1. SSPxSTAT 35.9.2. SSPxCON1 35.9.3. SSPxCON2 35.9.4. SSPxCON3 35.9.5. SSPxBUF 35.9.6. SSPxADD 35.9.7. SSPxMSK 36. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter 36.1. EUSART Asynchronous Mode 36.1.1. EUSART Asynchronous Transmitter 36.1.1.1. Enabling the Transmitter 36.1.1.2. Transmitting Data 36.1.1.3. Transmit Data Polarity 36.1.1.4. Transmit Interrupt Flag 36.1.1.5. TSR Status 36.1.1.6. Transmitting 9-Bit Characters 36.1.1.7. Asynchronous Transmission Setup 36.1.2. EUSART Asynchronous Receiver 36.1.2.1. Enabling the Receiver 36.1.2.2. Receiving Data 36.1.2.3. Receive Interrupts 36.1.2.4. Receive Framing Error 36.1.2.5. Receive Overrun Error 36.1.2.6. Receiving 9-Bit Characters 36.1.2.7. Address Detection 36.1.2.8. Asynchronous Reception Setup 36.1.2.9. 9-Bit Address Detection Mode Setup 36.1.3. Clock Accuracy with Asynchronous Operation 36.2. EUSART Baud Rate Generator (BRG) 36.2.1. Auto-Baud Detect 36.2.2. Auto-Baud Overflow 36.2.3. Auto-Wake-up on Break 36.2.3.1. Special Considerations 36.2.4. Break Character Sequence 36.2.4.1. Break and Sync Transmit Sequence 36.2.5. Receiving a Break Character 36.3. EUSART Synchronous Mode 36.3.1. Synchronous Master Mode 36.3.1.1. Master Clock 36.3.1.2. Clock Polarity 36.3.1.3. Synchronous Master Transmission 36.3.1.4. Synchronous Master Transmission Setup 36.3.1.5. Synchronous Master Reception 36.3.1.6. Receive Overrun Error 36.3.1.7. Receiving 9-Bit Characters 36.3.1.8. Synchronous Master Reception Setup 36.3.2. Synchronous Slave Mode 36.3.2.1. Slave Clock 36.3.2.2. EUSART Synchronous Slave Transmit 36.3.2.3. Synchronous Slave Transmission Setup 36.3.2.4. EUSART Synchronous Slave Reception 36.3.2.5. Synchronous Slave Reception Setup: 36.4. EUSART Operation During Sleep 36.4.1. Synchronous Receive During Sleep 36.4.2. Synchronous Transmit During Sleep 36.5. Register Summary - EUSART 36.6. Register Definitions: EUSART Control 36.6.1. RCxSTA 36.6.2. TXxSTA 36.6.3. BAUDxCON 36.6.4. SPxBRG 36.6.5. RCxREG 36.6.6. TXxREG 37. (SMT) Signal Measurement Timer 37.1. SMT Operation 37.1.1. Clock Source Selection 37.1.2. Signal and Window Source Selection 37.1.3. Time Base 37.1.4. Capture Pulse Width and Period Registers 37.1.5. Status Information 37.1.6. Modes of Operation 37.1.6.1. Timer Mode 37.1.6.2. Gated Timer Mode 37.1.6.3. Period and Duty Cycle Measurement Mode 37.1.6.4. High and Low Measurement Mode 37.1.6.5. Windowed Measurement Mode 37.1.6.6. Gated Window Measurement Mode 37.1.6.7. Time of Flight Measurement Mode 37.1.6.8. Capture Mode 37.1.6.9. Counter Mode 37.1.6.10. Gated Counter Mode 37.1.6.11. Windowed Counter Mode 37.1.7. Interrupts 37.1.8. Operation During Sleep 37.2. Register Summary - SMT Control 37.3. Register Definitions: SMT Control 37.3.1. SMTxCON0 37.3.2. SMTxCON1 37.3.3. SMTxSTAT 37.3.4. SMTxCLK 37.3.5. SMTxWIN 37.3.6. SMTxSIG 37.3.7. SMTxTMR 37.3.8. SMTxCPR 37.3.9. SMTxCPW 37.3.10. SMTxPR 38. Register Summary 39. In-Circuit Serial Programming™ (ICSP™) 39.1. High-Voltage Programming Entry Mode 39.2. Low-Voltage Programming Entry Mode 39.3. Common Programming Interfaces 40. Instruction Set Summary 40.1. Read-Modify-Write Operations 40.2. Standard Instruction Set 40.2.1. Standard Instruction Set
 41. Development Support 41.1. MPLAB X Integrated Development Environment Software 41.2. MPLAB XC Compilers 41.3. MPASM Assembler 41.4. MPLINK Object Linker/MPLIB Object Librarian 41.5. MPLAB Assembler, Linker and Librarian for Various Device Families 41.6. MPLAB X SIM Software Simulator 41.7. MPLAB REAL ICE In-Circuit Emulator System 41.8. MPLAB ICD 3 In-Circuit Debugger System 41.9. PICkit 3 In-Circuit Debugger/Programmer 41.10. MPLAB PM3 Device Programmer 41.11. Demonstration/Development Boards, Evaluation Kits, and Starter Kits 41.12. Third-Party Development Tools 42. Electrical Specifications 42.1. Absolute Maximum Ratings(†) 42.2. Standard Operating Conditions 42.3. DC Characteristics 42.3.1. Supply Voltage 42.3.2. Supply Current (IDD)(1,2,4) 42.3.3. Power-Down Current (IPD)(1,2) 42.3.4. I/O Ports 42.3.5. Memory Programming Specifications 42.3.6. Thermal Characteristics 42.4. AC Characteristics 42.4.1. External Clock/Oscillator Timing Requirements 42.4.2. Internal Oscillator Parameters(1) 42.4.3. PLL Specifications 42.4.4. I/O and CLKOUT Timing Specifications 42.4.5. Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications 42.4.6. Temperature Indicator Requirements 42.4.7. Analog-To-Digital Converter (ADC) Accuracy Specifications(1,2) 42.4.8. Analog-to-Digital Converter (ADC) Conversion Timing Specifications 42.4.9. Comparator Specifications 42.4.10. 5-Bit DAC Specifications 42.4.11. Fixed Voltage Reference (FVR) Specifications 42.4.12. Zero-Cross Detect (ZCD) Specifications 42.4.13. Timer0 and Timer1 External Clock Requirements 42.4.14. Capture/Compare/PWM Requirements (CCP) 42.4.15. Configurable Logic Cell (CLC) Characteristics 42.4.16. EUSART Synchronous Transmission Requirements 42.4.17. EUSART Synchronous Receive Requirements 42.4.18. SPI Mode Requirements 42.4.19. I2C Bus Start/Stop Bits Requirements 42.4.20. I2C Bus Data Requirements 43. DC and AC Characteristics Graphs and Tables 43.1. Graphs 44. Packaging Information 44.1. Package Details 45. Revision A (02/2018) The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service