Datasheet KS8995MA, KS8995FQ (Microchip) - 10
| Hersteller | Microchip |
| Beschreibung | Integrated 5-Port 10/100 Managed Switch |
| Seiten / Seite | 89 / 10 — List of Tables |
| Dateiformat / Größe | PDF / 1.1 Mb |
| Dokumentensprache | Englisch |
List of Tables
Modelllinie für dieses Datenblatt
Textversion des Dokuments
Micrel, Inc. KS8995MA/FQ
List of Tables
Table 1. MII − P5 Signals (PHY Mode) ... 34 Table 2. MII − SW Signals ... 35 Table 3. SNI Signals ... 36 Table 5. STPID Egress Rules (Processor to Switch Port 5) ... 38 Table 6. STPID Egress Rules (Switch to Processor) .. 38 Table 7. FID+DA Look-Up in the VLAN Mode .. 40 Table 8. FID+SA Look-Up in the VLAN Mode .. 40 Table 9. SPI Connections ... 44 Table 10. EEPROM Timing Parameters ... 79 Table 11. SNI Timing Parameters ... 80 Table 12. MAC Mode MII Timing Parameters ... 81 Table 13. PHY Mode MII Timing Parameters ... 82 Table 14. SPI Input Timing Parameters .. 83 Table 15. SPI Output Timing Parameters ... 84 Table 16. Reset Timing Parameters ... 85 Table 17. Qualified Magnetic Vendors .. 87 December 2012 10 M9999-121212-3.0
List of Tables
Table 1. MII − P5 Signals (PHY Mode) ... 34 Table 2. MII − SW Signals ... 35 Table 3. SNI Signals ... 36 Table 5. STPID Egress Rules (Processor to Switch Port 5) ... 38 Table 6. STPID Egress Rules (Switch to Processor) .. 38 Table 7. FID+DA Look-Up in the VLAN Mode .. 40 Table 8. FID+SA Look-Up in the VLAN Mode .. 40 Table 9. SPI Connections ... 44 Table 10. EEPROM Timing Parameters ... 79 Table 11. SNI Timing Parameters ... 80 Table 12. MAC Mode MII Timing Parameters ... 81 Table 13. PHY Mode MII Timing Parameters ... 82 Table 14. SPI Input Timing Parameters .. 83 Table 15. SPI Output Timing Parameters ... 84 Table 16. Reset Timing Parameters ... 85 Table 17. Qualified Magnetic Vendors .. 87 December 2012 10 M9999-121212-3.0