Datasheet KSZ8863MLL, KSZ8863FLL, KSZ8863RLL (Microchip) - 6

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KSZ8863MLL/FLL/RLL TABLE 2-1: SIGNALS Pin Pin Type Description Number Name Note 2-1
1 RXM1 I/O Physical receive or transmit signal (– differential) 2 RXP1 I/O Physical receive or transmit signal (+ differential) 3 TXM1 I/O Physical transmit or receive signal (– differential) 4 TXP1 I/O Physical transmit or receive signal (+ differential) 5 VDDA_3.3 P 3.3V analog VDD Set physical transmit output current. 6 ISET O Pull down this pin with an 11.8 kΩ 1% resistor to ground. 7 VDDA_1.8 P 1.8V analog core power input from VDDCO (pin 42). 8 RXM2 I/O Physical receive or transmit signal (– differential) 9 RXP2 I/O Physical receive or transmit signal (+ differential) 10 AGND GND Analog ground 11 TXM2 I/O Physical transmit or receive signal (– differential) 12 TXP2 I/O Physical transmit or receive signal (+ differential) 13 NC NC No connection 25 MHz or 50 MHz crystal or oscillator clock connections. 14 X1 I Pins (X1 and X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator, and X2 is a NC. Note: The clock is ±50 ppm for both crystal and oscillator. The clock should 15 X2 O be applied to X1 pin before the reset voltage goes high. 16 SMTXEN3 Ipu Switch MII transmit enable MLL/FLL: Switch MII transmit data bit 3 RLL: 17 SMTXD33/ Ipu
Strap option:
RMII mode Clock selection EN_REFCLKO_3 PU = Enable REFCLKO_3 output PD = Disable REFCLKO_3 output Switch MII transmit data bit 2 RLL:
Strap option:
X1 pin Clock selection (for Rev A3 and behind A3) 18 SMTXD32 Ipu PU = 25 MHz to X1 pin as clock source (default) PD = 50 MHz to X1 pin as clock source to provide or receive 50 MHz RMII reference clock for RLL part 19 SMTXD31 Ipu Switch MII/RMII transmit data bit 1 20 SMTXD30 Ipu Switch MII/RMII transmit data bit 0 21 GND GND Digital ground 3.3V, 2.5V, or 1.8V digital V 22 VDDIO P DD input power supply for IO with well decou- pling capacitors MLL/FLL: Switch MII transmit clock (MII and SNI modes only) Output in PHY MII mode and SNI mode SMTXC3/ Input in MAC MII and RMII mode 23 I/O REFCLKI_3 RLL: Reference clock input Note: Pull-down by resistor is needed if the internal reference clock is used in RLL by register 198 bit 3. Switch port 3 MII transmit error in MII mode SMTXER3/ 24 Ipd 0 = MII link indicator from host in MII PHY mode MII_LINK_3 1 = No link on port 3 MII PHY mode and enable bypass mode DS00002335B-page 6  2017 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power Management 3.3 MAC and Switch 3.4 Advanced Switch Functions 3.5 Spanning Tree Support 3.6 Rapid Spanning Tree Support 3.7 Tail Tagging Mode 3.8 IGMP Support 3.9 Port Mirroring Support 3.10 Rate Limiting Support 3.11 Unicast MAC Address Filtering 3.12 Configuration Interface 3.13 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Memory Map (8-Bit Registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-198) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 MAC Mode MII Timing 7.3 PHY Mode MII Timing 7.4 RMII Timing 7.5 I2C Slave Mode Timing 7.6 SPI Timing 7.7 Auto-Negotiation Timing 7.8 MDC/MDIO Timing 7.9 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History Product Identification System Worldwide Sales and Service