Datasheet AD8039-EP (Analog Devices) - 5

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AD8039-EP ABSOLUTE MAXIMUM RATINGS 2.0 Table 3. ) Parameter Rating (W
Supply Voltage 12.6 V
N 1.5 IO T
Power Dissipation See Figure 3
8-LEAD IPA SOIC_N
Common-Mode Input Voltage ±V
S
S
IS
Differential Input Voltage ±4 V
D R 1.0 E
Storage Temperature Range −65°C to +125°C
W O
Operating Temperature Range −55°C to +105°C
M P
Lead Temperature (Soldering, 10 sec) 300°C
MU 0.5 XI MA
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress
0
3
–55 –25 5 35 65 95 125
00 7- rating only; functional operation of the device at these or any
AMBIENT TEMPERATURE (°C)
55 09 other conditions above those indicated in the operational Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board section of this specification is not implied. Exposure to absolute RMS output voltages should be considered. If RL is referenced to maximum rating conditions for extended periods may affect −VS, as in single-supply operation, then the total drive power is device reliability. VS × IOUT. If the rms signal levels are indeterminate, consider the
MAXIMUM POWER DISSIPATION
worst case, when VOUT = VS/4 for RL to midsupply. The maximum safe power dissipation in the AD8039-EP PD = (VS × IS) + (VS/4)2/RL package is limited by the associated rise in junction temperature In single-supply operation with RL referenced to −VS, worst case (TJ) on the die. The plastic encapsulating the die locally reaches is VOUT = VS/2. the junction temperature. At approximately 150°C, which is the Airflow increases heat dissipation, effectively reducing θ glass transition temperature, the plastic changes its properties. JA. In addition, more metal directly in contact with the package Even temporarily exceeding this temperature limit may change leads from metal traces, throughholes, ground, and power the stresses that the package exerts on the die, permanently planes reduces θ shifting the parametric performance of the AD8039-EP. JA. Exceeding a junction temperature of 175°C for an extended Figure 3 shows the maximum safe power dissipation in the time can result in changes in the silicon devices, potentially package vs. the ambient temperature for the 8-lead SOIC_N causing failure. (125°C/W) on a JEDEC standard 4-layer board. θJA values are approximations. The still-air thermal properties of the package and PCB (θJA), ambient temperature (TA), and total power dissipated in the
OUTPUT SHORT CIRCUIT
package (PD) determine the junction temperature of the die. Shorting the output to ground or drawing excessive current The junction temperature can be calculated as from the AD8039-EP will likely cause a catastrophic failure. TJ = TA + (PD × θJA) The power dissipated in the package (PD) is the sum of the quies-
ESD CAUTION
cent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) multiplied by the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = quiescent power + (total drive power − load power) P 2 D = [VS × IS] + [(VS/2) × (VOUT/RL)] − [VOUT /RL] Rev. 0 | Page 5 of 8 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION OUTPUT SHORT CIRCUIT ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE