Datasheet AD8392A (Analog Devices) - 5

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AD8392A Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2.
RMS output voltages should be considered. If RL is referenced to
Parameter Rating
VS− as in single-supply operation, the total power is VS × IOUT. Supply Voltage ±13 V (+26 V) In single supply with RL to VS−, worst case is VOUT = VS/2. Power Dissipation See Figure 3 Storage Temperature Range −65°C to +150°C Airflow increases heat dissipation, effectively reducing θJA. In Operating Temperature Range −40°C to +85°C addition, more metal directly in contact with the package leads Lead Temperature (Soldering 10 sec) 300°C from metal traces, through holes, ground, and power planes Junction Temperature 150°C reduces the θJA. Stresses at or above those listed under Absolute Maximum Figure 3 shows the maximum safe power dissipation in the Ratings may cause permanent damage to the product. This is a package vs. the ambient temperature for the LFCSP-32 and stress rating only; functional operation of the product at these TSSOP_EP packages on a JEDEC standard 4-layer board. or any other conditions above those indicated in the operational θJA values are approximations. section of this specification is not implied. Operation beyond
7
the maximum operating conditions for extended periods may
TJ = 150°C
affect product reliability.
6 ) (W THERMAL RESISTANCE N 5 IO T
θ
LFCSP-32
JA is specified for the worst-case conditions, that is, θJA is specified
PA
for the device soldered in the circuit board for surface-mount
4 ISSI D
packages.
TSSOP-28/EP ER 3 W Table 3. M PO 2 MU Package Type θJA Unit XI 1
LFCSP-32 (CP) 27.27 °C/W
MA
TSSOP_EP (RE) 35.33 °C/W
0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
003
TEMPERATURE (°C) Maximum Power Dissipation
06477- Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the See the Thermal Considerations section for additional thermal package due to the load drive for al outputs. The quiescent design guidance. power is the voltage between the supply pins (VS) times the
ESD CAUTION
quiescent current (IS). Assuming that the load (RL) is midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). Rev. A | Page 4 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PIN CONFIGURATIONS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Maximum Power Dissipation ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS SUPPLIES, GROUNDING, AND LAYOUT POWER MANAGEMENT THERMAL CONSIDERATIONS TYPICAL ADSL/ADSL2+ APPLICATION MULTITONE POWER RATIO OUTLINE DIMENSIONS ORDERING GUIDE NOTES