Datasheet CD4070BMS, CD4077BMS (Intersil)
| Hersteller | Intersil |
| Beschreibung | CMOS Quad Exclusive OR and Exclusive NOR Gates |
| Seiten / Seite | 8 / 1 — Features. Pinouts. CD4070BMS. • High Voltage Types (20V Rating). A 1. 14 … |
| Revision | 2017-12-22 |
| Dateiformat / Größe | PDF / 271 Kb |
| Dokumentensprache | Englisch |
Features. Pinouts. CD4070BMS. • High Voltage Types (20V Rating). A 1. 14 VDD. • CD4070BMS - Quad Exclusive OR Gate. B 2. 13 H
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DATASHEET CD4070BMS, CD4077BMS FN3322 CMOS Quad Exclusive OR and Exclusive NOR Gates Rev 0.00 December 1992
Features Pinouts CD4070BMS
TOP VIEW
• High Voltage Types (20V Rating) A 1 14 VDD • CD4070BMS - Quad Exclusive OR Gate B 2 13 H • CD4077BMS - Quad Exclusive NOR Gate J = A
B 3 12 G • Medium Speed Operation K = C
D 4 11 M = G
H - tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pF C 5 10 L = E
F • 5V, 10V and 15V Parametric Ratings D 6 9 F VSS 7 8 E • Standardized, Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V CD4077BMS
TOP VIEW
• Maximum Input Current of 1
A at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC A 1 14 VDD • Noise Margin (Over Full Package/Temperature Range) B 2 13 H - 1V at VDD = 5V J = A
B 3 12 G - 2V at VDD = 10V K = CÝ
D 4 11 M = G
H - 2.5V at VDD = 15V C 5 10 L = E
F • Meets All Requirements of JEDEC Tentative Standard D 6 9 F No. 13B, “Standard Specifications for Description of VSS 7 8 E ‘B’ Series CMOS Devices” Applications Functional Diagram • Logical Comparators 1 A 3 • Parity Generators and Checkers 2 J B J = A
B • Adders/Subtractors K = C
D 5 C 4 6 K D M = G
H Description L = E
F 8 E 10
CD4070BMS contains four independent Exclusive OR
9 L VSS = 7 F
gates. The CD4077BMS contains four independent Exclu-
VDD = 14 12
sive NOR gates.
G 11 13 M H
The CD4070BMS and CD4077BMS provide the system designer with a means for direct implementation of the Exclusive OR and Exclusive NOR functions, respectively.
CD4070BMS
The CD4070BMS and CD4077BMS are supplied in these 14
1 A 3
lead outline packages:
2 J B
Braze Seal DIP H4Q
J = A
B 5 C 4 K = C
D 6 K
Frit Seal DIP H1B
D
Ceramic Flatpack *H4F †H3W
8 M = G
H E 10 9 L
*CD4070B Only †CD4077B Only
L = E
F F 12 G 11 13 M H CD4077BMS
FN3322 Rev 0.00 Page 1 of 8 December 1992
Features Pinouts CD4070BMS
TOP VIEW
• High Voltage Types (20V Rating) A 1 14 VDD • CD4070BMS - Quad Exclusive OR Gate B 2 13 H • CD4077BMS - Quad Exclusive NOR Gate J = A
B 3 12 G • Medium Speed Operation K = C
D 4 11 M = G
H - tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pF C 5 10 L = E
F • 5V, 10V and 15V Parametric Ratings D 6 9 F VSS 7 8 E • Standardized, Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V CD4077BMS
TOP VIEW
• Maximum Input Current of 1
A at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25oC A 1 14 VDD • Noise Margin (Over Full Package/Temperature Range) B 2 13 H - 1V at VDD = 5V J = A
B 3 12 G - 2V at VDD = 10V K = CÝ
D 4 11 M = G
H - 2.5V at VDD = 15V C 5 10 L = E
F • Meets All Requirements of JEDEC Tentative Standard D 6 9 F No. 13B, “Standard Specifications for Description of VSS 7 8 E ‘B’ Series CMOS Devices” Applications Functional Diagram • Logical Comparators 1 A 3 • Parity Generators and Checkers 2 J B J = A
B • Adders/Subtractors K = C
D 5 C 4 6 K D M = G
H Description L = E
F 8 E 10
CD4070BMS contains four independent Exclusive OR
9 L VSS = 7 F
gates. The CD4077BMS contains four independent Exclu-
VDD = 14 12
sive NOR gates.
G 11 13 M H
The CD4070BMS and CD4077BMS provide the system designer with a means for direct implementation of the Exclusive OR and Exclusive NOR functions, respectively.
CD4070BMS
The CD4070BMS and CD4077BMS are supplied in these 14
1 A 3
lead outline packages:
2 J B
Braze Seal DIP H4Q
J = A
B 5 C 4 K = C
D 6 K
Frit Seal DIP H1B
D
Ceramic Flatpack *H4F †H3W
8 M = G
H E 10 9 L
*CD4070B Only †CD4077B Only
L = E
F F 12 G 11 13 M H CD4077BMS
FN3322 Rev 0.00 Page 1 of 8 December 1992