Datasheet LT8364 (Analog Devices) - 7

LT8364
PIN FUNCTIONS EN/UVLO:
Shutdown and Undervoltage Detect Pin. The
RT:
A resistor from this pin to the exposed pad GND cop- LT8364 is shut down when this pin is low and active per (near FBX) programs switching frequency. when this pin is high. Below an accurate 1.6V threshold,
SS:
Soft-Start Pin. Connect a capacitor from this pin to the part enters undervoltage lockout and stops switching. GND copper (near FBX) to control the ramp rate of induc- This allows an undervoltage lockout (UVLO) threshold to tor current during converter start-up. SS pin charging be programmed for system input voltage by resistively current is 2μA. An internal 220Ω MOSFET discharges this dividing down system input voltage to the EN/UVLO pin. pin during shutdown or fault conditions. An 80mV pin hysteresis ensures part switching resumes when the pin exceeds 1.68V. EN/UVLO pin voltage below
SYNC/MODE:
This pin allows five selectable modes for 0.2V reduces VIN current below 1µA. If shutdown and optimization of performance. UVLO features are not required, the pin can be tied directly
SYNC/MODE Pin Input Capable Mode(s) of Operation
to system input. (1) GND or <0.14V Burst
VIN:
Input Supply. This pin must be locally bypassed. Be (2) External Clock Pulse-skip/Sync sure to place the positive terminal of the input capacitor as (3) 100k Resistor to GND Burst/SSFM close as possible to the VIN pin, and the negative terminal (4) Float (pin open) Pulse-skip as close as possible to the exposed pad PGND copper (5) INTVCC or >1.7V Pulse-skip/SSFM (near EN/UVLO). where the selectable modes of operation are,
INTVCC:
Regulated 3.2V Supply for Internal Loads. The INTV Burst = low IQ, low output ripple operation at light loads CC pin must be bypassed with a 1µF low ESR ceramic capacitor to GND. No additional components or loading is Pulse-skip = skipped pulse(s) at light load (aligned to clock) allowed on this pin. INTV Sync = switching frequency synchronized to external clock CC draws power from the BIAS pin if 4.4V ≤ BIAS ≤ V SSFM = Spread Spectrum Frequency Modulation for low IN, otherwise INTVCC is powered by the V EMI IN pin.
NC:
No Internal Connection. Leave this pin open.
SW1, SW2 (SW):
Output of the Internal Power Switch. Minimize the metal trace area connected to these pins to
BIAS:
Second Input Supply for Powering INTVCC. reduce EMI. Removes the majority of INTVCC current from the VIN pin to improve efficiency when 4.4V ≤ BIAS ≤ V
PGND,GND:
Power Ground and Signal Ground for the IN. If unused, tie the pin to GND. IC. The package has an exposed pad underneath the IC which is the best path for heat out of the package. The
VC:
Error Amplifier Output Pin. Tie external compensation pin should be soldered to a continuous copper ground network to this pin. plane under the device to reduce die temperature and
FBX:
Voltage Regulation Feedback Pin for Positive or increase the power capability of the LT8364. Connect Negative Outputs. Connect this pin to a resistor divider power ground components to the exposed pad copper between the output and the exposed pad GND copper exiting near the EN/UVLO and SW pins. Connect signal (near FBX). FBX reduces the switching frequency during ground components to the exposed pad copper exiting start-up and fault conditions when FBX is close to 0V. near the VC and FBX pins. 8364f For more information www.linear.com/LT8364 7 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION TYPICAL APPLICATION RELATED PARTS