Datasheet TC4421A, TC4422A (Microchip) - 9

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TC4421A/TC4422A 3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE Pin No. Pin No. Pin No. 8-Pin PDIP, Symbol Description 8-Pin DFN 5-Pin TO-220 SOIC
1 1 — VDD Supply input, 4.5V to 18V 2 2 1 INPUT Control input, TTL/CMOS-compatible input 3 3 — NC No connection 4 4 2 GND Ground 5 5 4 GND Ground 6 6 5 OUTPUT CMOS push-pull output 7 7 — OUTPUT CMOS push-pull output 8 8 3 VDD Supply input, 4.5V to 18V — PAD — NC Exposed metal pad — — TAB VDD Metal tab is at the VDD potential
3.1 Supply Input (VDD) 3.3 CMOS Push-Pull Output
The VDD input is the bias supply for the MOSFET driver The MOSFET driver output is a low-impedance, and is rated for 4.5V to 18V with respect to the ground CMOS, push-pull style output capable of driving a pin. The VDD input should be bypassed to ground with capacitive load with 9.0A peak currents. The MOSFET a local ceramic capacitor. The value of the capacitor driver output is capable of withstanding 1.5A peak should be chosen based on the capacitive load that is reverse currents of either polarity. being driven. A minimum value of 1.0 µF is suggested.
3.4 Ground 3.2 Control Input
The ground pins are the return path for the bias current The MOSFET driver input is a high-impedance, and for the high peak currents that discharge the load TTL/CMOS-compatible input. The input also has capacitor. The ground pins should be tied into a ground 300 mV of hysteresis between the high and low plane or have very short traces to the bias supply thresholds that prevents output glitching even when the source return. rise and fall time of the input signal is very slow.
3.5 Exposed Metal Pad
The exposed metal pad of the 6x5 DFN package is not internally connected to any potential. Therefore, this pad can be connected to a ground plane or other copper plane on a Printed Circuit Board (PCB) to aid in heat removal from the package.
3.6 Metal Tab
The metal tab of the TO-220 package is connected to the VDD potential of the device. This connection to VDD can be used as a current carrying path for the device.  2005-2013 Microchip Technology Inc. DS21946B-page 9 Document Outline 1.0 Electrical Characteristics 2.0 Typical Performance Curves FIGURE 2-1: Rise Time vs. Supply Voltage. FIGURE 2-2: Rise Time vs. Capacitive Load. FIGURE 2-3: Fall Time vs. Supply Voltage. FIGURE 2-4: Fall Time vs. Capacitive Load. FIGURE 2-5: Rise and Fall Times vs. Temperature. FIGURE 2-6: Crossover Energy vs Supply Voltage. FIGURE 2-7: Propagation Delay vs. Supply Voltage. FIGURE 2-8: Propagation Delay vs. Input Amplitude. FIGURE 2-9: Propagation Delay vs. Temperature. FIGURE 2-10: Quiescent Supply Current vs. Supply Voltage. FIGURE 2-11: Quiescent Supply Current vs. Temperature. FIGURE 2-12: Input Threshold vs. Temperature. FIGURE 2-13: Input Threshold vs. Supply Voltage. FIGURE 2-14: High-State Output Resistance vs. Supply Voltage. FIGURE 2-15: Low-State Output Resistance vs. Supply Voltage. FIGURE 2-16: Supply Current vs. Capactive Load (VDD = 18V). FIGURE 2-17: Supply Current vs. Capactive Load (VDD = 12V). FIGURE 2-18: Supply Current vs. Capactive Load (VDD = 6V). FIGURE 2-19: Supply Current vs. Frequency (VDD = 18V). FIGURE 2-20: Supply Current vs. Frequency (VDD = 12V). FIGURE 2-21: Supply Current vs. Frequency (VDD = 6V). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Supply Input (VDD) 3.2 Control Input 3.3 CMOS Push-Pull Output 3.4 Ground 3.5 Exposed Metal Pad 3.6 Metal Tab 4.0 Applications Information FIGURE 4-1: Switching Time Test Circuits. 5.0 Packaging Information 5.1 Package Marking Information Corporate Office Atlanta Boston Chicago Cleveland Fax: 216-447-0643 Dallas Detroit Indianapolis Toronto Fax: 852-2401-3431 Australia - Sydney China - Beijing China - Shanghai India - Bangalore Korea - Daegu Korea - Seoul Singapore Taiwan - Taipei Fax: 43-7242-2244-393 Denmark - Copenhagen France - Paris Germany - Munich Italy - Milan Spain - Madrid UK - Wokingham Worldwide Sales and Service