Datasheet AD8450 (Analog Devices) - 10

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Data Sheet AD8450 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS L H P FLS N O H E EF EF AX ND EF CC AV R VEE AV AV INT VEE CS IM O IS ISR AG ISR VR A ISMEA AV O O ISET NC IVE0 IVE1 NC V A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ISVP 1 60 VCLP RGP PIN 1 2 59 VCTRL RGPS 3 58 VCLN ISGP0 4 57 AVCC ISGP0S 5 56 VINT ISGP1 6 55 NC ISGP1S 7 54 VVE1 ISGP2 8 53 VVE0 AD8450 ISGP3 9 52 NC TOP VIEW RFBP 10 (Not to Scale) 51 VVP0 RFBN 11 50 VSETBF ISGN3 12 49 VSET ISGN2 13 48 NC ISGN1S 14 47 DVCC ISGN1 15 46 FAULT ISGN0S 16 45 DGND ISGN0 17 44 OCPS RGNS 18 43 OCPR RGN 19 42 VREF ISVN 20 41 OVPR 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 H L S 3S EF F F L N0 N1 N2 N3 DE P VP3 VP2 VP1 VP0 ND F CC N3S VEE VPS B B B B O VR RE RE BV BV BV BV A O BV AG RE AV BV VMEA M B BV BV BV
002
NOTES 1. NC = NO CONNECT.
1966- 1 Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Input/ Pin No. Mnemonic Output1 Description
1, 20 ISVP, ISVN Input Current Sense Instrumentation Amplifier Positive (Noninverting) and Negative (Inverting) Inputs. Connect these pins across the current sense shunt resistor. 2, 19 RGP, RGN N/A Current Sense Instrumentation Amplifier Gain Setting Pins. Connect these pins to the appropriate resistor network gain pins to select the current sense gain (see Table 5). 3, 18 RGPS, RGNS N/A Kelvin Sense Pins for the Current Sense Instrumentation Amplifier Gain Setting Pins (RGP and RGN). 4, 6, ISGP0, ISGP1, N/A Current Sense Instrumentation Amplifier Resistor Network Gain Pins (see Table 5). 8, 9, ISGP2, ISGP3, 12, 13, ISGN3, ISGN2, 15, 17 ISGN1, ISGN0 5, 7, ISGP0S, ISGP1S, N/A Kelvin Sense Pins for the ISGP0, ISGP1, ISGN1, and ISGN0 Pins. 14, 16 ISGN1S, ISGN0S 10, 11 RFBP, RFBN Output Current Sense Preamplifier Positive and Negative Outputs. 21, 35 BVP3S, BVN3S N/A Kelvin Sense Pins for the Voltage Sense Difference Amplifier Inputs BVP3 and BVN3. 22, 23, BVP3, BVP2, Input Voltage Sense Difference Amplifier Inputs. Each input pair (BVPx and BVNx) corresponds to a 24, 25, BVP1, BVP0, different voltage sense gain (see Table 6). 31, 32, BVN0, BVN1, 33, 34 BVN2, BVN3 26, 42, 73 VREF Output Voltage Reference Output Pins. VREF = 2.5 V. 27 BVREFH Input Reference Input for the Voltage Sense Difference Amplifier. To level shift the voltage sense difference amplifier output by approximately 5 mV, connect this pin to the VREF pin. Otherwise, connect this pin to the BVREFL pin. 28, 75 AGND N/A Analog Ground Pins. 29 BVREFL Input Reference Input for the Voltage Sense Difference Amplifier. The default connection is to ground. 30 BVREFLS N/A Kelvin Sense Pin for the BVREFL Pin. Rev. B | Page 9 of 41 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS PGIA CHARACTERISTICS PGDA CHARACTERISTICS CC AND CV LOOP FILTER AMPLIFIERS, UNCOMMITTED OP AMP, AND VSET BUFFER VINT BUFFER CURRENT SHARING AMPLIFIER COMPARATORS REFERENCE CHARACTERISTICS THEORY OF OPERATION INTRODUCTION PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER (PGIA) Gain Selection Reversing Polarity When Charging and Discharging PGIA Offset Option Battery Reversal and Overvoltage Protection PROGRAMMABLE GAIN DIFFERENCE AMPLIFIER (PGDA) CC AND CV LOOP FILTER AMPLIFIERS COMPENSATION VINT BUFFER MODE PIN, CHARGE AND DISCHARGE CONTROL OVERCURRENT AND OVERVOLTAGE COMPARATORS CURRENT SHARING BUS AND IMAX OUTPUT APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION POWER SUPPLY CONNECTIONS POWER SUPPLY SEQUENCING POWER-ON SEQUENCE POWER-OFF SEQUENCE PGIA CONNECTIONS Current Sensors Optional Low-Pass Filter PGDA CONNECTIONS Reverse Battery Conditions BATTERY CURRENT AND VOLTAGE CONTROL INPUTS (ISET AND VSET) LOOP FILTER AMPLIFIERS CONNECTING TO A PWM CONTROLLER (VCTRL PIN) OVERVOLTAGE AND OVERCURRENT COMPARATORS STEP BY STEP DESIGN EXAMPLE Step 1: Design the Switching Power Converter Step 2: Identify the Control Voltage Range of the ADP1972 Step 3: Determine the Control Voltage for the CV Loop and the PGDA Gain Step 4: Determine the Control Voltage for the CC Loop, the Shunt Resistor, and the PGIA Gain Step 5: Choose the Control Voltage Sources Step 6: Select the Compensation Devices ADDITIONAL INFORMATION EVALUATION BOARD INTRODUCTION FEATURES AND TESTS TESTING THE AD8450-EVALZ PGIA and Offset PGIA Gain Test PGIA in an Application Simple Offset Test Offset in an Application PGDA and Offset Simple Test PGDA in an Application PGDA Offset Overload Comparators VSET Buffer CV and CC Loop Filter Amplifiers CC and CV Integrator Tests Uncommitted Op Amp USING THE AD8450 SCHEMATIC AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE