Datasheet ADXRS450 (Analog Devices) - 7

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ADXRS450 Data Sheet I S SS DD SS SVD P P MO DV CS VX R 14 13 12 11 10 9 8 1 2 3 4 5 6 7 O K 5 SS DD S DD L CP AV AV SVD MI DV SC R
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TOP VIEW
0 2-
(Not to Scale)
95 08 Figure 4. LCC_V Pin Configuration
K 5 L DD DD SS SVD SO R CP SC DV MI AV AV 7 6 5 4 3 2 1 8 9 10 11 12 13 14 I S VX CS SS SS DD SVD P P R DV MO (Not to Scale) NOTES 1. THE LCC_V PACKAGE HAS TWO TERMINALS ON TWO FACES; HOWEVER, THE TERMINALS ON THE BACK SIDE ARE FOR INTERNAL EVALUATION ONLY AND SHOULD NOT BE USED IN THE END APPLICATION. THE TERMINALS ON THE BOTTOM OF THE PACKAGE INCORPORATE METALLIZATION BUMPS THAT ENSURE A MINIMUM SOLDER THICKNESS FOR IMPROVED SOLDER JOINT RELIABILITY. THESE BUMPS ARE NOT
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PRESENT ON THE BACK SIDE TERMINALS AND, THEREFORE, POOR SOLDER JOINT RELIABILITY CAN BE
0 2-
ENCOUNTERED IF USED IN THE END APPLICATION. SEE THE OUTLINE DIMENSIONS SECTION FOR A
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SCHEMATIC OF THE LCC_V PACKAGE.
08 Figure 5. LCC_V Pin Configuration, Horizontal Layout
Table 5. 14-Lead LCC_V Pin Function Descriptions Pin No. Mnemonic Description
1 AVSS Analog Ground. 2 AVDD Analog Regulated Voltage. See Figure 20 for the applications circuit diagram. 3 MISO Master In/Slave Out. 4 DVDD Digital Regulated Voltage. See Figure 20 for the applications circuit diagram. 5 SCLK SPI Clock. 6 CP5 High Voltage Supply. See Figure 20 for the applications circuit diagram. 7 RSVD Reserved. This pin must be connected to DVSS. 8 RSVD Reserved. This pin must be connected to DVSS. 9 VX High Voltage Switching Node. See Figure 20 for the applications circuit diagram. 10 CS Chip Select. 11 DVSS Digital Signal Ground. 12 MOSI Master Out/Slave In. 13 PSS Switching Regulator Ground. 14 PDD Supply Voltage. Rev. C | Page 6 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings Thermal Resistance Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Continuous Self-Test Applications Information Mechanical Considerations for Mounting Applications Circuits ADXRS450 Signal Chain Timing SPI Communication Protocol Command/Response SPI Communications Characteristics SPI Applications Device Data Latching Command/Response—Bit Definitions SQ2 to SQ0 SM2 to SM0 A8 to A0 D15 to D0 SPI ST1 to ST0 P P0 P1 RE DU Fault Register Bit Definitions PLL Q NVM POR PWR CST CHK OV UV Fail Amp K-Bit Assertion: Recommended Start-Up Routine SPI Rate Data Format Memory Map and Registers Memory Map Memory Register Definitions Rate Registers Temperature (TEMx) Registers Low CST (LOCST) Memory Registers High CST (HICST) Memory Registers Quad Memory Registers Fault Registers Part ID (PID) Registers Serial Number (SN) Registers Dynamic Null Correction (DNC) Registers Package Orientation and Layout Information Package Marking Codes Outline Dimensions Ordering Guide