Datasheet ADXRS645 (Analog Devices) - 6

Data Sheet ADXRS645 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ST1 ST2 TEMP 3 A B C UT O E IO 5 ND MJ DD G RAT CP V P RAT SU V 2 A B C D E F 1 A B C D E F 3 4 1 2 CC ND CP CP CP CP AV AG ADXRS645
003
TOP VIEW (Not to Scale)
1958- 1 Figure 3. Pin Configuration (Top View) 200 11958- Figure 4. Pin Configuration (3D View)
Table 3. Pin Function Descriptions Pin Number Mnemonic Description
A1 CP3 Charge Pump Capacitor, 22 nF A2 CP5 HV Filter Capacitor, 100 nF A3 ST1 Positive Self-Test B1 CP4 Charge Pump Capacitor, 22 nF B2 VDD Positive Charge Pump Supply B3 ST2 Negative Self-Test C1 CP1 Charge Pump Capacitor, 22 nF C2 PGND Charge Pump Supply Return C3 TEMP Temperature Voltage Output D1 CP2 Charge Pump Capacitor, 22 nF D2 RATEOUT Rate Signal Output E1 AVCC Positive Analog Supply E2 SUMJ Output Amplifier Summing Junction F1 AGND Analog Supply Return F2 VRATIO Reference Supply for Ratiometric Output Rev. A | Page 5 of 10 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Rate Sensitive Axis ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Setting Bandwidth Temperature Output and Calibration Supply Ratiometricity Range Extension Self-Test Function Continuous Self-Test Outline Dimensions Ordering Guide