Datasheet ADXRS290 (Analog Devices) - 6

Data Sheet ADXRS290 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS S /O MX T G DD I RE PD SEN AS V V 5 4 3 2 1 PDMY 6 18 VS CS 7 17 VREG ADXRS290 TOP VIEW (TERMINAL SIDE DOWN) MISO 8 16 GND Not to Scale MOSI 9 15 GND 10 11 12 13 14 K S CP ND V CL SEL G S /A C
003
SYN
12636- Figure 3. Pin Configuration (Top View)
Table 4. Pin Function Descriptions Description Pin No. Mnemonic Digital Mode Analog Evaluation Mode
1 VREG Regulator Output. Connect a 1 µF capacitor to this pin. Regulator Output. Connect a 1 µF capacitor to this pin. 2 VDD I/O Digital Interface Supply Voltage. Digital Interface Supply Voltage. 3 AST This pin is internally pulled to ground. Self Test. 4 SENS This pin is internally pulled to ground. Sensitivity Select. 5 PDMX This pin is internally pulled to ground. Pulse-Density Modulation (PDM) XOUT. 6 PDMY This pin is internally pulled to ground. PDM YOUT. 7 CS Chip Select. Active low. Chip Select. Active low. 8 MISO (SDO) Serial Data Out. Serial Data Out. 9 MOSI (SDI) Serial Data In. Serial Data In. 10 SCLK Serial Communications Clock. Serial Communications Clock. 11 SYNC/ASEL Data Ready Out (SYNC). Connect this pin to ground if Analog Enable (ASEL). it is not used. 12 CP Charge Pump Output. Connect a 1 µF capacitor (rated Charge Pump Output. Connect a 1 µF capacitor (rated for 50 V) to this pin. for 50 V) to this pin. 13, 15, 16 GND Ground. Connect to ground. Ground. Connect to ground. 14 VS Analog Supply Voltage. Analog Supply Voltage. 17 VREG Regulator Output. Connect a 1 µF capacitor to this pin. Regulator Output. Connect a 1 µF capacitor to this pin. 18 VS Analog Supply Voltage. Analog Supply Voltage. Rev. A | Page 5 of 19 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATE SENSITIVE AXES PACKAGE INFORMATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION APPLICATION CIRCUIT POWER SUPPLY DECOUPLING POWER SEQUENCING SETTING BANDWIDTH Offset Preservation in the High-Pass Filter ANALOG EVALUATION MODE MECHANICAL CONSIDERATIONS FOR MOUNTING SERIAL COMMUNICATIONS REGISTER MAP REGISTER DESCRIPTIONS ANALOG DEVICES IDENTIFIER MEMS IDENTIFIER DEVICE IDENTIFIER SILICON REVISION NUMBER SERIAL NUMBER (SNx) RATE OUTPUT DATA Register 0x08 to Register 0x0B: DATAX0, DATAX1, DATAY0, and DATAY1 (Read Only) TEMPERATURE DATA Register 0x0C to Register 0x0D: TEMP0 and TEMP1 (Read Only) POWER CONTROL TSM Bit Measurement Bit BAND-PASS FILTER LPF Bits HPF Bits DATA READY Sync Bits RECOMMENDED SOLDERING PROFILE PCB FOOTPRINT PATTERN OUTLINE DIMENSIONS ORDERING GUIDE