Datasheet ADIS16362 (Analog Devices) - 10

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Data Sheet ADIS16362 THEORY OF OPERATION BASIC OPERATION
The user registers provide addressing for al input/output opera- The ADIS16362 is an autonomous sensor system that starts up tions on the SPI interface. Each 16-bit register has two 7-bit after it has a valid power supply voltage and begins producing addresses: one for its upper byte and one for its lower byte. inertial measurement data at the factory default sample rate Table 8 lists the lower byte address for each register, and Figure 10 setting of 819.2 SPS. After each sample cycle, the sensor data is shows the generic bit assignments. loaded into the output registers, and DIO1 pulses high, which
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
provides a new data ready control signal for driving system- 010
UPPER BYTE LOWER BYTE
level interrupt service routines. In a typical system, a master 08179- Figure 10. Generic Register Bit Assignments processor accesses the output data registers through the SPI interface, using the connection diagram shown in Figure 9.
READING SENSOR DATA
Table 6 provides a generic functional description for each pin Although the ADIS16362 produces data independently, it oper- on the master processor. Table 7 describes the typical master ates as a SPI slave device that communicates with system (master) processor settings that are normal y found in a configuration processors using the 16-bit segments displayed in Figure 11. register and used for communicating with the ADIS16362. Individual register reads require two of these 16-bit sequences. The
I/O LINES ARE COMPATIBLE WITH
first 16-bit sequence provides the read command bit (R/W = 0)
5V 3.3V OR 5V LOGIC LEVELS VDD
and the target register address (A6 to A0). The second sequence
10 11 12
transmits the register contents (D15 to D0) on the DOUT line.
SYSTEM
For example, if DIN = 0x0A00, the contents of XACCL_OUT are
PROCESSOR SS 6 CS ADIS16362 SPI MASTER SPI SLAVE
shifted out on the DOUT line during the next 16-bit sequence.
SCLK 3 SCLK
The SPI operates in ful -duplex mode, which means that the master
MOSI 5 DIN
processor can read the output data from DOUT while using the
MISO 4 DOUT
same SCLK pulses to transmit the next target address on DIN.
IRQ 7 DIO1 DEVICE CONFIGURATION 13 14 15
009 The user register memory map (see Table 8) identifies configu- 08179- ration registers with either a W or R/W. Configuration commands Figure 9. Electrical Connection Diagram also use the bit sequence shown in Figure 11. If the MSB = 1, the
Table 6. Generic Master Processor Pin Names and Functions
last eight bits (DC7 to DC0) in the DIN sequence are loaded into
Pin Name Function
the memory address associated with the address bits (A6 to A0). SS Slave select For example, if DIN = 0xA11F, 0x1F is loaded into Address 0x21 IRQ Interrupt request (XACCL_OFF, upper byte) at the conclusion of the data frame. MOSI Master output, slave input The master processor initiates the backup function by setting MISO Master input, slave output GLOB_CMD[3] = 1 (DIN = 0xBE08). This command copies SCLK Serial clock the user registers into their assigned flash memory locations and requires the power supply to stay within its normal operating
Table 7. Generic Master Processor SPI Settings
range for the entire 50 ms process. The FLASH_CNT register
Processor Setting Description
provides a running count of these events for monitoring the Master The ADIS16362 operates as a slave long-term reliability of the flash memory. SCLK Rate ≤ 2 MHz1 Normal mode, SMPL_PRD[7:0] ≤ 0x09 SPI Mode 3 CPOL = 1 (polarity), CHPA = 1 (phase) MSB First Mode Bit sequence 16-Bit Mode Shift register/data length 1 For burst read, SCLK rate ≤ 1 MHz. For low power mode, SCLK rate ≤ 300 kHz.
CS SCLK DIN R/W R/W A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 A6 A5 DOUT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 NOTES
011
1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0.
08179- Figure 11. SPI Communication Bit Sequence Rev. E | Page 9 of 20 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Basic Operation Reading Sensor Data Device Configuration Memory Map Burst Read Data Collection Output Data Registers Calibration Manual Bias Calibration Gyroscope Automatic Bias Null Calibration Gyroscope Precision Automatic Bias Null Calibration Restoring Factory Calibration Linear Acceleration Bias Compensation (Gyroscope) Operational Control Global Commands Internal Sample Rate Power Management Sensor Bandwidth Digital Filtering Dynamic Range Input/Output Functions General-Purpose I/O Input Clock Configuration Data Ready I/O Indicator Auxiliary DAC Diagnostics Self-Test Memory Test Status Alarm Registers Product Identification Applications Information Installation/Handling Gyroscope Bias Optimization Input ADC Channel Interface Printed Circuit Board (PCB) Outline Dimensions Ordering Guide