Datasheet AD7741, AD7742 (Analog Devices) - 3

AD7741/AD7742 (VDD = +4.75 V to +5.25 V; VREF = +2.5 V; fCLKIN = 6.144 MHz; all specifications TMIN to AD7742–SPECIFICATIONS TMAX unless otherwise noted.) B Version1 Y Version2 Parameter3 Min Typ Max Min Typ Max Units Conditions/Comments
DC PERFORMANCE Integral Nonlinearity fCLKIN = 200 kHz4 ± 0.0122 ± 0.015 % of Span5 fCLKIN = 3 MHz4 ± 0.0122 ± 0.015 % of Span fCLKIN = 6.144 MHz ± 0.0122 ± 0.015 % of Span Offset Error ± 40 ± 40 mV Unipolar Mode ± 40 ± 40 mV Bipolar Mode Gain Error +0.2 +1.2 +2.2 +0.2 +1.2 +2.2 % of Span Unipolar Mode +0.2 +1.2 +2.2 +0.2 +1.2 +2.2 % of Span Bipolar Mode Offset Error Drift4 ± 12 ± 12 µV/°C Unipolar Mode ± 12 ± 12 µV/°C Bipolar Mode Gain Error Drift4 ± 2 ± 2 ppm of Span/°C Unipolar Mode ± 4 ± 4 ppm of Span/°C Bipolar Mode Power Supply Rejection Ratio4 –70 –70 dB ∆VDD = ±5% Channel-to-Channel Isolation4 –75 –75 dB Common-Mode Rejection –60 –78 –58 –78 dB ANALOG INPUTS (VIN1–VIN4)6 Input Current ± 50 ± 100 ± 50 ± 100 nA Common-Mode Input Range +0.5 VDD – 1.75 +0.5 VDD – 1.75 V Differential Input Range –VREF/Gain +VREF/Gain –VREF/Gain +VREF/Gain V Bipolar Mode 0 +VREF/Gain 0 +VREF/Gain V Unipolar Mode VOLTAGE REFERENCE REFIN Nominal Input Voltage 2.5 2.5 V Input Impedance4 fCLKIN = 3 MHz 70 70 kΩ fCLKIN = 6.144 MHz 35 35 kΩ REFOUT Output Voltage 2.38 2.50 2.60 2.38 2.50 2.60 V Output Impedance4 1 1 kΩ Reference Drift4 ± 50 ± 50 ppm/°C Line Rejection –70 –70 dB Reference Noise (0.1 Hz to 10 Hz)4 100 100 µV p-p LOGIC OUTPUT Output High Voltage, VOH 4.0 4.0 V Output Sourcing 800 µA7 Output Low Voltage, VOL 0.4 0.4 V Output Sinking 1.6 mA7 Minimum Output Frequency 0.05 fCLKIN 0.05 fCLKIN Hz VIN = 0 V (Unipolar), VIN = –VREF/Gain (Bipolar) Maximum Output Frequency 0.45 fCLKIN 0.45 fCLKIN Hz VIN = VREF/Gain (Unipolar and Bipolar) LOGIC INPUT ALL EXCEPT CLKIN Input High Voltage, VIH 2.4 2.4 V Input Low Voltage, VIL 0.8 0.8 V Input Current ± 100 ± 100 nA Pin Capacitance 6 10 6 10 pF CLKIN ONLY Input High Voltage, VIH 3.5 3.5 V Input Low Voltage, VIL 0.8 0.8 V Input Current ± 2 ± 2 µA Pin Capacitance 6 10 6 10 pF CLOCK FREQUENCY Input Frequency 6.144 6.144 MHz For Specified Performance POWER REQUIREMENTS VDD 4.75 5.25 4.75 5.25 V IDD (Normal Mode) 6 8 6 8 mA Output Unloaded IDD (Power-Down) 25 35 25 35 µA Power-Up Time4 30 30 µs Coming Out of Power- Down Mode NOTES 1Temperature range: B Version: –40°C to +85°C. 2Temperature range: Y Version: –40°C to +105°C. 3See Terminology. 4Guaranteed by design and characterization, not production tested. 5Span = Maximum Output Frequency–Minimum Output Frequency. 6The absolute voltage on the input pins must not go more positive than VDD – 1.75 V or more negative than +0.5 V. 7These logic levels apply to CLKOUT only when it is loaded with one CMOS load. Specifications subject to change without notice. REV. 0 –3–