Datasheet ADIS16203 (Analog Devices) - 6

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ADIS16203 TIMING SPECIFICATIONS
TA = +25°C, VDD = 3.3 V, tilt = 0°, unless otherwise noted.
Table 2. Parameter Description Min1 Typ Max Unit
fSCLK Fast mode, SMPL_TIME ≤ 0x07 (fS ≥ 1024 Hz) 0.01 2.5 MHz Normal mode, SMPL_TIME ≥ 0x08 (fS ≤ 910 Hz) 0.01 1.0 MHz tDATARATE Chip select period, fast mode, SMPL_TIME ≤ 0x07 (fS ≥ 1024 Hz) 40 μs Chip select period, normal mode, SMPL_TIME ≥ 0x08 (fS ≤ 910 Hz) 100 μs tCS Chip select to clock edge 48.8 ns tDAV Data output valid after SCLK falling edge2 100 ns tDSU Data input setup time before SCLK rising edge 24.4 ns tDHD Data input hold time after SCLK rising edge 48.8 ns tDF Data output fall time 5 12.5 ns tDR Data output rise time 5 12.5 ns tSFS CS high after SCLK edge3 5 ns 1 Guaranteed by design, not production tested. 2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and are governed by this specification. 3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
TIMING DIAGRAMS tDATARATE tSTALL CS SCLK
02 0 8-
tSTALL = tDATARATE – 16/fSCLK
10 06 Figure 2. SPI Chip Select Timing
CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN W/R A5 A4 A3 A2 D2 D1 LSB
03 0 8- 10 06 Figure 3. SPI Timing, Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1 Rev. A | Page 5 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMACE CHARACTERISTICS THEORY OF OPERATION OUTPUT RESPONSE TEMPERATURE SENSOR BASIC OPERATION SERIAL PERIPHERAL INTERFACE (SPI) DATA OUTPUT REGISTER ACCESS PROGRAMMING AND CONTROL CONTROL REGISTER OVERVIEW CONTROL REGISTER ACCESS CONTROL REGISTER DETAILS CALIBRATION CALIBRATION REGISTER DEFINITION INCL_NULL Register Definition ALARMS ALM_MAG1 Register Definition ALM_SMPL1 Register Definition ALM_MAG2 Register Definition ALM_SMPL2 Register Definition ALM_CTRL Register Definition SAMPLE PERIOD CONTROL SMPL_TIME Register Definition FILTERING CONTROL AVG_CNT Register Definition POWER-DOWN CONTROL SLP_CNT Register Definition STATUS FEEDBACK STATUS Register Definition COMMAND CONTROL COMMAND Register Definition MISCELLANEOUS CONTROL REGISTER MSC_CTRL Register Definition PERIPHERALS AUXILIARY ADC FUNCTION AUXILIARY DAC FUNCTION AUX_DAC Register Definition GENERAL-PURPOSE I/O CONTROL GPIO_CTRL Register Definition APPLICATIONS HARDWARE CONSIDERATIONS GROUNDING AND BOARD LAYOUT RECOMMENDATIONS SELF-TEST TIPS BAND GAP REFERENCE POWER-ON RESET OPERATION SECOND-LEVEL ASSEMBLY EXAMPLE PAD LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE