Datasheet ADXL375 (Analog Devices) - 7

ADXL375 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADXL375 TOP VIEW (Not to Scale) SCL/SCLK V 1 14 13 SDA/SDI/SDIO DD I/O GND 2 12 SDO/ALT ADDRESS RESERVED 3 11 RESERVED +X GND 4 10 NC +Y +Z GND 5 9 INT2 V 6 7 8 INT1 S CS
002
NOTES 1. NC = NOT INTERNALLY CONNECTED.
1669- 1 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VDD I/O Digital Interface Supply Voltage. 2 GND Ground. This pin must be connected to ground. 3 RESERVED Reserved. This pin must be connected to VS or left open. 4 GND Ground. This pin must be connected to ground. 5 GND Ground. This pin must be connected to ground. 6 VS Supply Voltage. 7 CS Chip Select. 8 INT1 Interrupt 1 Output. 9 INT2 Interrupt 2 Output. 10 NC Not Internally Connected. 11 RESERVED Reserved. This pin must be connected to ground or left open. 12 SDO/ALT ADDRESS SPI 4-Wire Serial Data Output (SDO)/I2C Alternate Address Select (ALT ADDRESS). 13 SDA/SDI/SDIO I2C Serial Data (SDA)/SPI 4-Wire Serial Data Input (SDI)/SPI 3-Wire Serial Data Input and Output (SDIO). 14 SCL/SCLK I2C Serial Communications Clock (SCL)/SPI Serial Communications Clock (SCLK). Rev. B | Page 6 of 32 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Soldering Profile Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Power Sequencing Current Consumption and Output Data Rate Power Saving Modes Low Power Mode Autosleep Mode Standby Mode FIFO Buffer Bypass Mode FIFO Mode Stream Mode Trigger Mode Retrieving Data from the FIFO Buffer Self-Test Interrupts Enabling and Disabling Interrupts Clearing Interrupts Bits in the Interrupt Registers DATA_READY Bit SINGLE_SHOCK Bit DOUBLE_SHOCK Bit Activity Bit Inactivity Bit Watermark Bit Overrun Bit Serial Communications SPI Mode Preventing Bus Traffic Errors I2C Mode Register Map Register Descriptions Register 0x00—DEVID (Read Only) Register 0x1D—THRESH_SHOCK (Read/Write) Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Register 0x21—DUR (Read/Write) Register 0x22—Latent (Read/Write) Register 0x23—Window (Read/Write) Register 0x24—THRESH_ACT (Read/Write) Register 0x25—THRESH_INACT (Read/Write) Register 0x26—TIME_INACT (Read/Write) Register 0x27—ACT_INACT_CTL (Read/Write) ACT AC/DC and INACT AC/DC Bits ACT_x Enable and INACT_x Enable Bits Register 0x2A—SHOCK_AXES (Read/Write) Suppress Bit SHOCK_x Enable Bits Register 0x2B—ACT_SHOCK_STATUS (Read Only) ACT_x Source and SHOCK_x Source Bits Asleep Bit Register 0x2C—BW_RATE (Read/Write) LOW_POWER Bit Rate Bits Register 0x2D—POWER_CTL (Read/Write) Link Bit AUTO_SLEEP Bit Measure Bit Sleep Bit Wakeup Bits Register 0x2E—INT_ENABLE (Read/Write) Register 0x2F—INT_MAP (Read/Write) Register 0x30—INT_SOURCE (Read Only) Register 0x31—DATA_FORMAT (Read/Write) SELF_TEST Bit SPI Bit INT_INVERT Bit Justify Bit Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only) Register 0x38—FIFO_CTL (Read/Write) FIFO_MODE Bits Trigger Bit Samples Bits Register 0x39—FIFO_STATUS (Read Only) FIFO_TRIG Bit Entries Bits Applications Information Power Supply Decoupling Mechanical Considerations for Mounting Shock Detection Threshold Detection and Bandwidth Link Mode Sleep Mode vs. Low Power Mode Offset Calibration Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz Using Self-Test Axes of Acceleration Sensitivity Layout and Design Recommendations Package Information Outline Dimensions Ordering Guide