Datasheet MCP73831, MCP73832 (Microchip) - 8
Hersteller | Microchip |
Beschreibung | Miniature Single-Cell, Fully Integrated Li-Ion, Li-Polymer Charge Management Controllers |
Seiten / Seite | 28 / 8 — MCP73831/2. TYPICAL PERFORMANCE CURVES (CONTINUED). Note:. 104. 525. … |
Revision | 07-14-2014 |
Dateiformat / Größe | PDF / 843 Kb |
Dokumentensprache | Englisch |
MCP73831/2. TYPICAL PERFORMANCE CURVES (CONTINUED). Note:. 104. 525. RPROG = 10 kΩ. RPROG = 2 kΩ. ) 103. 450. 102. m 375. t (. n 101. 300. rre 100
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MCP73831/2 TYPICAL PERFORMANCE CURVES (CONTINUED) Note:
Unless otherwise indicated, VDD = [VREG(typical) + 1V], IOUT = 10 mA and TA= +25°C, Constant-Voltage mode.
104 525 RPROG = 10 kΩ RPROG = 2 kΩ ) 103 450 A A) 102 (m m 375 t t ( n 101 300 rre 100 rren u 225 Cu e C 99 e rg 150 arg 98 a h C 97 Ch 75 96 0 0 0 0 0 0 -4 -3 -2 -1 10 20 30 40 50 60 70 80 25 35 45 55 65 75 85 95 105 115 125 135 145 155 Ambient Temperature (°C) Junction Temperature (°C) FIGURE 2-7:
Charge Current (IOUT) vs.
FIGURE 2-10:
Charge Current (IOUT) vs. Ambient Temperature (TA). Junction Temperature (TJ).
516 0 R V PROG = 2 kΩ AC = 100 mVp-p 514 ) IOUT = 10 mA A -10 512 COUT = 4.7 µF, X7R Ceramic (m B) d 510 -20 ( n rrent 508 u tio -30 a 506 u ge C -40 ten ar 504 h At C 502 -50 500 -60 0 -40 -30 -20 -10 10 20 30 40 50 60 70 80 0.01 0.1 1 10 100 1000 Ambient Temperature (°C) Frequency (kHz) FIGURE 2-8:
Charge Current (IOUT) vs.
FIGURE 2-11:
Power Supply Ripple Ambient Temperature (TA). Rejection (PSRR).
120 0 R V PROG = 10 kΩ AC = 100 mVp-p 105 I A) -10 OUT = 100 mA m 90 ) COUT = 4.7 µF, X7R Ceramic t ( B 75 d -20 n ( rren 60 o -30 ati e Cu 45 rg -40 a 30 ttenu A Ch 15 -50 0 -60 25 35 45 55 65 75 85 95 105 115 125 135 145 155 0.01 0.1 1 10 100 1000 Junction Temperature (°C) Frequency (kHz) FIGURE 2-9:
Charge Current (IOUT) vs.
FIGURE 2-12:
Power Supply Ripple Junction Temperature (TJ). Rejection (PSRR). DS20001984G-page 8 2005-2014 Microchip Technology Inc. Document Outline MCP73831/2 Functional Block Diagram 1.0 Electrical Characteristics 2.0 Typical Performance Curves FIGURE 2-1: Battery Regulation Voltage (VBAT) vs. Supply Voltage (VDD). FIGURE 2-2: Battery Regulation Voltage (VBAT) vs. Ambient Temperature (TA). FIGURE 2-3: Output Leakage Current (IDISCHARGE) vs. Battery Regulation Voltage (VBAT). FIGURE 2-4: Charge Current (IOUT) vs. Programming Resistor (RPROG). FIGURE 2-5: Charge Current (IOUT) vs. Supply Voltage (VDD). FIGURE 2-6: Charge Current (IOUT) vs. Supply Voltage (VDD). FIGURE 2-7: Charge Current (IOUT) vs. Ambient Temperature (TA). FIGURE 2-8: Charge Current (IOUT) vs. Ambient Temperature (TA). FIGURE 2-9: Charge Current (IOUT) vs. Junction Temperature (TJ). FIGURE 2-10: Charge Current (IOUT) vs. Junction Temperature (TJ). FIGURE 2-11: Power Supply Ripple Rejection (PSRR). FIGURE 2-12: Power Supply Ripple Rejection (PSRR). FIGURE 2-13: Line Transient Response. FIGURE 2-14: Line Transient Response. FIGURE 2-15: Load Transient Response. FIGURE 2-16: Load Transient Response. FIGURE 2-17: Complete Charge Cycle (180 mAh Li-Ion Battery). FIGURE 2-18: Complete Charge Cycle (1000 mAh Li-Ion Battery). 3.0 Pin Description TABLE 3-1: Pin Function TableS 3.1 Battery Management Input Supply (VDD) 3.2 Battery Charge Control Output (VBAT) 3.3 Charge Status Output (STAT) 3.4 Battery Management 0V Reference (VSS) 3.5 Current Regulation Set (PROG) 3.6 Exposed Thermal Pad (EP) 4.0 Device Overview FIGURE 4-1: Flowchart. 4.1 Undervoltage Lockout (UVLO) 4.2 Battery Detection 4.3 Charge Qualification 4.4 Preconditioning 4.5 Fast Charge Constant-Current Mode 4.6 Constant-Voltage Mode 4.7 Charge Termination 4.8 Automatic Recharge 4.9 Thermal Regulation FIGURE 4-2: Thermal Regulation. 4.10 Thermal Shutdown 5.0 Detailed Description 5.1 Analog Circuitry 5.2 Digital Circuitry TABLE 5-1: Status Output 6.0 Applications FIGURE 6-1: Typical Application Circuit. FIGURE 6-2: Typical Charge Profile (180 mAh Battery). FIGURE 6-3: Typical Charge Profile in Thermal Regulation (1000 mAh Battery). 6.1 Application Circuit Design 6.2 PCB Layout Issues FIGURE 6-4: Typical Layout (Top). FIGURE 6-5: Typical Layout (Bottom). 7.0 Packaging Information 7.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales