Datasheet LTC4401-1, LTC4401-2 (Analog Devices) - 8

LTC4401-1/LTC4401-2
U U W U APPLICATIO S I FOR ATIO Enable:
When SHDN is asserted high the part will auto-
Power Ramp Profiles
matically calibrate out all offsets. This takes <10µs and is The external voltage gain associated with the RF channel controlled by an internal delay circuit. After 10µs VPCA/B can vary significantly between RF power amplifier types. will step up to the starting voltage of 450mV. The user can The LTC4401-X frequency compensation has been then apply the ramp signal. The user should wait 12µs after optimized to be stable with several different power ampli- SHDN has been asserted high before applying the ramp. fiers and manufacturers. This frequency compensation The DAC should be settled 2µs after asserting SHDN high. generally defines the loop dynamics that impact the power/ time response and possibly (slow loops) the power ramp
LTC4401-X Timing Diagram
sidebands. The LTC4401-X operates open loop until an RF T7 T8 voltage appears at the RF pin, at which time the loop closes BSEL (LTC4401-2 ONLY) and the output power follows the DAC profile. The RF 2µs 543µs 10µs 28µs 28µs power amplifier will require a certain control voltage level (threshold) before an RF output signal is produced. The SHDN LTC4401-X VPCA/B output(s) must quickly rise to this threshold voltage in order to meet the power/time profile. VPCA/B To reduce this time, the LTC4401-X starts at 450mV. VSTART However, at very low power levels the PCTL input signal is PCTL small, and the VPCA/B output may take several microsec- onds to reach the RF power amplifier threshold voltage. To 4400 TA02 T1 T2 T3 T4 T5 T6 reduce this time, it may be necessary to apply a positive T1: LTC4401-X COMES OUT OF SHUTDOWN 12 pulse at the start of the ramp to quickly bring the V µs PRIOR TO BURST PCA/B T2: INTERNAL TIMER COMPLETES AUTOZERO CORRECTION, <10µs output to the threshold voltage. This can generally be T3: BASEBAND CONTROLLER STARTS RF POWER RAMP UP AT 12µs AFTER SHDN IS ASSERTED HIGH achieved with DAC programming. The magnitude of the T4: BASEBAND CONTROLLER COMPLETES RAMP UP T5: BASEBAND CONTROLLER STARTS RF POWER RAMP DOWN AT END OF BURST pulse is dependent on the RF amplifier characteristics. T6: LTC4401-X RETURNS TO SHUTDOWN MODE BETWEEN BURSTS T7: BSEL CHANGE PRIOR TO SHDN, 0ns TYPICAL (LTC4401-2 ONLY) Power ramp sidebands and power/time are also a factor T8: BSEL CHANGE AFTER TO SHDN, 0ns TYPICAL (LTC4401-2 ONLY) when ramping to zero power. When the power is ramped down the loop will eventually open at power levels below
General Layout Considerations
the LTC4401-X detector threshold. The LTC4401-X will The LTC4401-X should be placed near the directional then go open loop and the output voltage at VPCA/B will coupler. The feedback signal line to the RF pin should be stop falling. If this voltage is high enough to produce RF a 50Ω transmission line with optional termination or a output power, the power/time or power ramp sidebands short line. may not meet specification. This problem can be avoided by starting the DAC ramp from 200mV (Figure 1). At the
External Termination
end of the cycle, the DAC can be ramped down to 0mV. The LTC4401-X has an internal 250Ω termination resistor This applies a negative signal to the LTC4401-X thereby at the RF pin. If a directional coupler is used, it is recom- ensuring that the VPCA/B output will ramp to 0V. The mended that an external 68Ω termination resistor be 200mV ramp step must be applied < 2µs after SHDN is connected between the RF coupling capacitor (33pF), and asserted high to allow the autozero to cancel the step. Slow ground at the side connected to the directional coupler. DAC rise times will extend this time by the additional RC Termination components should be placed adjacent to the time constants which may require that the DAC is enabled LTC4401-X. and settled prior to SHDN asserted high. 4401fa 8