Datasheet LT5537 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Wide Dynamic Range RF/IF Log Detector |
| Seiten / Seite | 16 / 7 — PI FU CTIO S. ENBL (Pin 1):. VCC (Pin 6):. VEE (Pin 7):. IN+, IN– (Pins … |
| Dateiformat / Größe | PDF / 315 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. ENBL (Pin 1):. VCC (Pin 6):. VEE (Pin 7):. IN+, IN– (Pins 2, 3):. OUT (Pin 8):. Exposed Pad (Pin 9):
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LT5537
U U U PI FU CTIO S ENBL (Pin 1):
Enable Pin. When the input voltage is higher
VCC (Pin 6):
Power Supply Pin. This pin should be decoupled than 1V, the circuit is ON. When the input voltage is less than using 1000pF and 0.1µF capacitors. 0.3V, or this pin is not connected, the chip is disabled (OFF).
VEE (Pin 7):
Ground pin.
IN+, IN– (Pins 2, 3):
Differential Signal Input Pins. These
OUT (Pin 8):
Output pin. pins are internally biased to VCC – 0.4V. The impedance between IN+ and IN– is approximately 1.73kΩ//1.45pF at
Exposed Pad (Pin 9):
Should be connected to PCB ground. 200MHz. The input pins should be AC coupled.
CAP+, CAP– (Pins 4, 5):
External Filter Capacitor Pins. The minimum RF input frequency can be lowered by adding an optional external capacitor between CAP+ and CAP–.
W BLOCK DIAGRA
4 5 7k CAP+ CAP– 7k OFFSET VCC 6 CANCELLATION IN+ 2 IN– 3 OUTPUT OUT DETECTOR CELLS 8 BUFFER 7.2k VEE 7 ENBL BANDGAP REFERENCE 1 AND BIASING EXPOSED PAD 7 5537 BD 5537fa 7
U U U PI FU CTIO S ENBL (Pin 1):
Enable Pin. When the input voltage is higher
VCC (Pin 6):
Power Supply Pin. This pin should be decoupled than 1V, the circuit is ON. When the input voltage is less than using 1000pF and 0.1µF capacitors. 0.3V, or this pin is not connected, the chip is disabled (OFF).
VEE (Pin 7):
Ground pin.
IN+, IN– (Pins 2, 3):
Differential Signal Input Pins. These
OUT (Pin 8):
Output pin. pins are internally biased to VCC – 0.4V. The impedance between IN+ and IN– is approximately 1.73kΩ//1.45pF at
Exposed Pad (Pin 9):
Should be connected to PCB ground. 200MHz. The input pins should be AC coupled.
CAP+, CAP– (Pins 4, 5):
External Filter Capacitor Pins. The minimum RF input frequency can be lowered by adding an optional external capacitor between CAP+ and CAP–.
W BLOCK DIAGRA
4 5 7k CAP+ CAP– 7k OFFSET VCC 6 CANCELLATION IN+ 2 IN– 3 OUTPUT OUT DETECTOR CELLS 8 BUFFER 7.2k VEE 7 ENBL BANDGAP REFERENCE 1 AND BIASING EXPOSED PAD 7 5537 BD 5537fa 7