Datasheet LTC4317 (Analog Devices) - 9

HerstellerAnalog Devices
BeschreibungDual I2C/SMBus Address Translator
Seiten / Seite16 / 9 — operaTion System Configurations. Setting the Translation Byte. Figure 4. …
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operaTion System Configurations. Setting the Translation Byte. Figure 4. Two Slaves Sharing One Channel of LTC4317

operaTion System Configurations Setting the Translation Byte Figure 4 Two Slaves Sharing One Channel of LTC4317

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LTC4317
operaTion System Configurations
7-bit translation byte. These voltages are referenced to There are several ways that individual slaves or banks of VCC so a resistive divider at each of these pins is the most slaves can be connected to an LTC4317. In Figure 3, each convenient way to set the voltages. The required transla- slave is paired with one channel of the LTC4317. This tion byte can be determined by taking the bitwise XOR of configuration allows for maximum flexibility in allocating the slave’s original address and the desired input address. the bus addresses. Both read and write operations and all The voltages at the XORH and XORL pins configure the protocols supported by the LTC4317 are allowed. Figure 4 translation byte. The XORL voltage configures the lower 4 shows two slaves with different hardwired addresses translation bits (excluding the R/W bit), while the XORH translated to two different addresses using one channel of voltage configures the upper 3 translation bits. Tables 2 the LTC4317 and a common translation byte. A program and 3 show the recommended resistive divider values. RLT is available to help the user visualize an I2C bus with the and RLB are the top and bottom resistors connected to LTC4317; this program can be found in the following link: XORL, while RHT and RHB are the top and bottom resistors www.linear.com/TranslatorTool connected to XORH (Figure 5). Use 1% tolerance resistors for RLT, RLB, RHT and RHB.
Setting the Translation Byte
When the LTC4317 is first powered up or any time a rising edge is detected on the ENABLE pin, the LTC4317 reads SCL the voltages at the XORH and XORL pins to determine the SLAVE #2 SDA HARDWIRED ADDRESS SLAVE #1 0x34 INPUT ADDRESS SCL 0x32 SCLIN SCLOUT SCL TRANSLATION BYTE MASTER 00110110 0x06 SLAVE SDA LTC4317 00000010 #1 00110100 SCLIN SCLOUT1 SCL SDAIN SDAOUT SDA 00110010 SLAVE LTC4317 00000110 HARDWIRED ADDRESS #1 TRANSLATION BYTE 00110100 0x02 0x34 SDAIN SDAOUT1 SDA SLAVE #1 SCL HARDWIRED ADDRESS INPUT ADDRESS 00110010 0x34 0x36 SLAVE 00000010 #3 SLAVE #3 00110000 SCLOUT2 SCL INPUT ADDRESS SDA 00110110 SLAVE 0x32 00000010 HARDWIRED ADDRESS #3 00110100 0x30 SDAOUT2 SDA 4317 F04 HARDWIRED ADDRESS
Figure 4. Two Slaves Sharing One Channel of LTC4317
SLAVE #3 INPUT ADDRESS 0x36 0x34 SCL TRANSLATION BYTE 0x02 V MASTER CC V SDA SCL CC RHT RLT SLAVE LTC4317 #2 XORH XORL SDA RHB RLB HARDWIRED ADDRESS 0x34 4317 F03 4317 F05
Figure 3. Two Independent Address Translation Figure 5. Address Translation Byte Configuration Resistors
4317fa For more information www.linear.com/LTC4317 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Timing Diagram Typical Performance Characteristics Pin Functions Block Diagram Operation Typical Applications Package Description Revision History Typical Application Related Parts