Datasheet LTC4314 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | Pin-Selectable, 4-Channel, 2-Wire Multiplexer with Bus Buffers |
| Seiten / Seite | 20 / 1 — FEATURES. DESCRIPTION. 1:4 Multiplexer/Switch for 2-Wire Bus. … |
| Dateiformat / Größe | PDF / 207 Kb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTION. 1:4 Multiplexer/Switch for 2-Wire Bus. Bidirectional Buffer for SDA and SCL Lines
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LTC4314 Pin-Selectable, 4-Channel, 2-Wire Multiplexer with Bus Buffers
FEATURES DESCRIPTION
n
1:4 Multiplexer/Switch for 2-Wire Bus
The LTC®4314 is a hot-swappable 4-channel 2-wire bus n
Bidirectional Buffer for SDA and SCL Lines
multiplexer that allows one upstream bus to connect to n
High Noise Margin with V
any combination of downstream busses or channels.
IL = 0.3•VCC
n
ENABLE Pins Connect SDA and SCL Lines
An individual enable pin controls each connection. The n
Selectable Rise Time Accelerator Current and
LTC4314 provides bidirectional buffering, keeping the up-
Activation Voltage
stream bus capacitance isolated from the downstream bus n Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses capacitances. The high noise margin allows the LTC4314 n to be interoperable with I2C devices that drive a high V Prevents SDA and SCL Corruption During Live Board OL (> 0.4V). The LTC4314 supports level translation between Insertion and Removal from Backplane n 1.5V, 1.8V, 2.5V, 3.3V and 5V busses. The hot-swappable Stuck Bus Disconnect and Recovery n nature of the LTC4314 allows I/O card insertion into, and Compatible with I2C, I2C Fast Mode and SMBus n removal from, a live backplane without corruption of the ±4kV Human Body Model (HBM) ESD Ruggedness n data and clock busses. 20-Lead SSOP and 3mm × 4mm QFN Packages If both data and clock are not simultaneously high at
APPLICATIONS
least once in 45ms and DISCEN is high, a FAULT signal is generated indicating a stuck bus low condition, the input n Telecommunications Systems Including ATCA is disconnected from all enabled output channels, and up n Address Expansion to 16 clocks are generated on the enabled downstream n Level Translator busses. A three state ACC pin enables input and output n Capacitance Buffers/Bus Extender side rise time accelerators of varying strengths and sets n Live Board Insertion the V n IL,RISING voltage. PMBus L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6356140, 6650174, 7032051, 7478286.
TYPICAL APPLICATION
3.3V 3.3V
Rising Edge from Asserted Low with Level Translation
0.01μF 0.01μF 10k 10k VCC VCC2 10k 10k 6V CSCLOUT1 + CSCLOUT4 = 100pF CSCLIN = 50pF SCLIN SCLIN SCLOUT4 5V SDAIN SDAIN ENABLE1 ENABLE1 SCLOUT1 SCLOUT1 ENABLE2 ENABLE2 SDAOUT1 SDAOUT1 SCLOUT1 3.3V ENABLE3 ENABLE3 •• •• /DIV 1V ENABLE4 ENABLE4 SCLIN 5V • • 3.3V LTC4314 10k 10k 10k ACC SCLOUT4 SCLOUT4 0V DISCEN SDAOUT4 SDAOUT4 200ns/DIV FAULT FAULT 4314 TA01b GND 4314 TA01a 4314f 1
FEATURES DESCRIPTION
n
1:4 Multiplexer/Switch for 2-Wire Bus
The LTC®4314 is a hot-swappable 4-channel 2-wire bus n
Bidirectional Buffer for SDA and SCL Lines
multiplexer that allows one upstream bus to connect to n
High Noise Margin with V
any combination of downstream busses or channels.
IL = 0.3•VCC
n
ENABLE Pins Connect SDA and SCL Lines
An individual enable pin controls each connection. The n
Selectable Rise Time Accelerator Current and
LTC4314 provides bidirectional buffering, keeping the up-
Activation Voltage
stream bus capacitance isolated from the downstream bus n Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses capacitances. The high noise margin allows the LTC4314 n to be interoperable with I2C devices that drive a high V Prevents SDA and SCL Corruption During Live Board OL (> 0.4V). The LTC4314 supports level translation between Insertion and Removal from Backplane n 1.5V, 1.8V, 2.5V, 3.3V and 5V busses. The hot-swappable Stuck Bus Disconnect and Recovery n nature of the LTC4314 allows I/O card insertion into, and Compatible with I2C, I2C Fast Mode and SMBus n removal from, a live backplane without corruption of the ±4kV Human Body Model (HBM) ESD Ruggedness n data and clock busses. 20-Lead SSOP and 3mm × 4mm QFN Packages If both data and clock are not simultaneously high at
APPLICATIONS
least once in 45ms and DISCEN is high, a FAULT signal is generated indicating a stuck bus low condition, the input n Telecommunications Systems Including ATCA is disconnected from all enabled output channels, and up n Address Expansion to 16 clocks are generated on the enabled downstream n Level Translator busses. A three state ACC pin enables input and output n Capacitance Buffers/Bus Extender side rise time accelerators of varying strengths and sets n Live Board Insertion the V n IL,RISING voltage. PMBus L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6356140, 6650174, 7032051, 7478286.
TYPICAL APPLICATION
3.3V 3.3V
Rising Edge from Asserted Low with Level Translation
0.01μF 0.01μF 10k 10k VCC VCC2 10k 10k 6V CSCLOUT1 + CSCLOUT4 = 100pF CSCLIN = 50pF SCLIN SCLIN SCLOUT4 5V SDAIN SDAIN ENABLE1 ENABLE1 SCLOUT1 SCLOUT1 ENABLE2 ENABLE2 SDAOUT1 SDAOUT1 SCLOUT1 3.3V ENABLE3 ENABLE3 •• •• /DIV 1V ENABLE4 ENABLE4 SCLIN 5V • • 3.3V LTC4314 10k 10k 10k ACC SCLOUT4 SCLOUT4 0V DISCEN SDAOUT4 SDAOUT4 200ns/DIV FAULT FAULT 4314 TA01b GND 4314 TA01a 4314f 1