Datasheet LTC4313-1, LTC4313-2, LTC4313-3 (Analog Devices) - 7

LTC4313-1/LTC4313-2/ LTC4313-3
operaTion
The LTC4313 is a high noise margin bus buffer which precharge circuit. RTAs for the LTC4313-1 and LTC4313-2 provides capacitance buffering for I2C signals. Capacitance are also enabled at this time. buffering is achieved by using back to back buffers on When a SDA/SCL pin is driven below the V the clock and data channels which isolate the SDAIN IL level, the buffers are turned on and the logic low level is propagated and SCLIN capacitances from the SDAOUT and SCLOUT though the LTC4313 to the other side. A high occurs when capacitances respectively. All SDA and SCL pins are fully all devices on the input and output sides release high. Once bidirectional. The high noise margin allows the LTC4313 to the bus voltages rise above the V operate with non-compliant I2C devices that drive a high IL level, the buffers are turned off. The RTAs are turned on at a slightly higher volt- VOL, permits a number of LTC4313s to be connected in age. The RTAs accelerate the rising edges of the SDA/SCL series and improves the reliability of I2C communications inputs and outputs up to a voltage of 0.9•V in large noisy systems. Rise time accelerator (RTA) pull-up CC, provided that the busses on their own are rising at a minimum rate currents (IRTA) turn on during rising edges to reduce bus of 0.4V/µs as determined by the slew rate detectors. The rise time for the LTC4313-1 and LTC4313-2. In a typical RTAs are configured to operate in a strong slew limited application the input and output busses are pulled up to switch mode in the LTC4313-1 and in the current source VCC although this is not a requirement. If VDD,BUS is not mode in the LTC4313-2. tied to VCC, VDD,BUS must be greater than VCC to prevent overdrive of the bus by the RTAs for the LTC4313-1 and The LTC4313 detects a bus stuck low (fault) condition LTC4313-2. See the Applications Information section for when both clock and data busses are not simultaneously VDD,BUS requirements for the LTC4313-3. high at least once in 45ms. When a stuck bus occurs, the LTC4313 disconnects the input and output sides and after When the LTC4313 first receives power on its VCC pin, it waiting at least 40µs, generates up to sixteen 5.5kHz clock starts out in an undervoltage lockout mode (UVLO) until pulses on the SCLOUT pin and a stop bit to attempt to free its VCC exceeds 2.7V. The buffers and RTAs are disabled the stuck bus. Should the stuck bus release high during and the LTC4313 ignores the logic state of its clock and this period, automatic clock generation is terminated. data pins. During this time the precharge circuit forces a nominal voltage of 1V on the SDA and SCL pins through Once the stuck bus recovers, connection is re-established 200k resistors. between the input and output after a stop bit or bus idle condition is detected. Toggling ENABLE after a fault condi- Once the LTC4313 exits UVLO and its ENABLE pin has tion has occurred forces a connection between the input been asserted high, it monitors the clock and data pins and output. When powering into a stuck low condition, the for a stop bit or a bus idle condition. When a combination input and output sides remain disconnected even after the of either condition is detected simultaneously on the input LTC4313 has exited the UVLO mode as a stop bit or bus and output sides, the LTC4313 activates the connection idle condition is not detected on the stuck busses. After between SDAIN and SDAOUT, and SCLIN and SCLOUT, the timeout period, a stuck low fault condition is detected respectively, asserts READY high and deactivates the and the behavior is as described previously. 4313123f 7 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts