Datasheet LTC4312 (Analog Devices) - 8

LTC4312
OPERATION
The Block Diagram shows the major functional blocks of the VCC and VCC2 voltages. For VCC2 < 1.8V, VMIN is the VCC LTC4312. The LTC4312 is a 1:2 multiplexer with capacitance voltage. The LTC4312 is designed to sink a minimum buffering for I2C signals. Capacitance buffering is achieved total bus current IOL of 4mA while holding a VOL of 0.4V. by use of back to back buffers on the clock and data chan- If multiple output channels are enabled, the bus current of nels which isolate the SDAIN and SCLIN capacitances from all enabled channels needs to be summed to get the total the SDAOUT and SCLOUT capacitances respectively. All bus current. See the Typical Performance Characteristics SDA and SCL pins are fully bidirectional. The high noise curves for IOL as a function of temperature. margin allows the LTC4312 to operate with I2C devices A high occurs when all devices on the input and output that drive a non-compliant high VOL. Multiplexing is done sides release high. Once the bus voltages rise above the using N-channel MOSFETs that are controlled by dedicated V ENABLE pins. When enabled, rise time accelerator pull-up IL, RISING level, which is determined by the state of the ACC pin, the buffers are turned off. The rise time accelerators currents IRTA turn on during rising edges to reduce sys- are turned on at a slightly higher voltage. The rise time tem rise time. In a typical application the input side bus accelerators accelerate the rising edges of the SDA/SCL is pulled up to VCC and the output side busses are pulled inputs and selected outputs up to voltages of 0.9•V up to V CC and CC2 although these are not requirements. VCC is 0.8•V the primary power supply to the LTC4312. V CC2 respectively, provided that the busses on their CC and VCC2 own are rising at a minimum rate of 0.2V/μs as determined serve as the input and output side rise time accelerator by the slew rate detectors. ACC is a 3-state input that con- supplies respectively. Grounding VCC2 disables the output trols V side accelerators. The multiplexer N-channel MOSFET IL,RISING , the rise time accelerator turn-on voltage and the rise time accelerator pull-up strength. gates of the enabled channels are driven to VCC2 if VCC2 is > 1.8V, otherwise they are driven to V The LTC4312 detects a bus stuck low (fault) condition CC. when both clock and data busses are not simultaneously When the LTC4312 fi rst receives power on its VCC pin, it high at least once in 45ms. The voltage monitoring for a starts out in an undervoltage lockout mode (UVLO) until stuck low condition is done on the common internal node 110μs after VCC exceeds 2.3V. During this time, the buffers of the clock and data outputs. Hence a stuck low condition and rise time accelerators are disabled, the multiplexer is detected only if it occurs on an enabled output channel. gates are off and the LTC4312 ignores transitions on the When a stuck bus occurs, the LTC4312 asserts the FAULT clock and data pins independent of the state of the ENABLE fl ag. If DISCEN is tied high, the LTC4312 also disconnects pins. VCC2 transitions from a high to a low or vice-versa the input and output sides. After waiting at least 40μs, it across a 1.8V threshold also cause the LTC4312 to dis- generates up to sixteen 5.5kHz clock pulses on the enabled able the buffers, rise time accelerators and transmission SCLOUT pins and a stop bit to attempt to free the stuck gates and to ignore the clock and data pins until 110μs bus. If the bus recovers high before 16 clocks are issued, after that transition. Assuming that the LTC4312 is not in the LTC4312 ceases issuing clocks and generates a stop UVLO mode, when one or both ENABLEs are asserted, bit. If DISCEN is tied low, a stuck bus event only causes the LTC4312 activates the connection circuitry between FAULT fl ag assertion. Disconnection of the input and output the SDAIN/SCLIN inputs and selected output channels. sides and clock generation do not occur. Once the stuck The input rise time accelerators and the output rise time bus recovers and the fault has been cleared, in order for a accelerators of the selected channels are also enabled at connection to be established between the input and output this time. When a SDA/SCL input pin or output pin on an sides, both ENABLE pins need to be driven low followed enabled output channel is driven below the VIL,FALLING by the assertion high of the desired ENABLE pins. When level of 0.33 • VMIN, the buffers are turned on and the powering into a stuck low condition, the LTC4312 upon logic low level is propagated though the LTC4312 to exiting UVLO will connect the input and output sides for the other side. For VCC2 > 1.8V, VMIN is the lower of the 45ms until a stuck bus timeout event is detected. 4312f 8