Datasheet LTC4308 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | Low Voltage, Level Shifting Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery |
| Seiten / Seite | 16 / 9 — OPERATION. Figure 2. Input-Output Rising Edge Waveforms. Figure 3. … |
| Dateiformat / Größe | PDF / 172 Kb |
| Dokumentensprache | Englisch |
OPERATION. Figure 2. Input-Output Rising Edge Waveforms. Figure 3. Input-Output Falling Edge Waveforms. Propagation Delays
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LTC4308
OPERATION
COUT = 50pF COUT = 50pF VPULLUP(OUT) = VCC = 3.3V VPULLUP(OUT) = VCC = 3.3V /DIV /DIV 1V 1V CIN = 150pF CIN = 150pF VPULLUP(IN) = 1.8V VPULLUP(IN) = 1.8V 200ns/DIV 200ns/DIV 4308 F02 4308 F03
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms Propagation Delays
output capacitances translate to longer delays. Users must quantify the difference in propagation times for a rising During a rising edge, the rise time on each side is infl u- edge versus a falling edge in their systems and adjust enced by rise time acceleration, bus pull-up resistor, and setup and hold times accordingly. the equivalent capacitance on the line. If the pull-up resis- tors are the same, a difference in rise time occurs which is
Bus Stuck Low Timeout
directly proportional to the difference in capacitance and SDAOUT and SCLOUT are each connected to an internal the presence of rise time acceleration between the two timer. When SDAOUT or SCLOUT is low, its respective sides. This effect is displayed in Figure 2 for VCC = 3.3V timer is started. Each timer is only reset when its pin goes and a 2.7k pull-up resistor on the input (VPULLUP(IN) = high. If the bus stuck low does not go high within 30ms 1.8V, CIN = 150pF) and output (VPULLUP(OUT) = 3.3V, COUT (typical), the connection circuitry is disabled, breaking = 50pF). Since the output pin has rise time acceleration the connection between the respective input and output and less capacitance than the input, it rises faster and pins. In addition, after at least 40μs, up to 16 clock pulses the effective propagation delay is negative. at 8.5kHz (typical) are generated on the SCLOUT pin by There is a fi nite propagation delay through the connec- the LTC4308 in an attempt to free the stuck low bus. The tion circuitry for falling waveforms. Figure 3 shows the clock pulses are halted if the bus recovers to a logic high falling edge waveforms for the same pull-up resistors and condition before the completion of the full 16 pulses. A equivalent capacitance conditions as used in Figure 2. stop bit is always generated on the SCLOUT and SDAOUT An external N-channel MOSFET device pulls down the pins to reset all devices on the bus. voltage on the side with 150pF capacitance; the LTC4308 If the stuck low SDAOUT or SCLOUT does not recover to pulls down the voltage on the opposite side with a delay a logic high condition after the automatic clocking and of 70ns. This delay is always positive and is a function of stop bit generation, the LTC4308 remains disconnected. supply voltage, temperature and the pull-up resistors and Should the bus free, the LTC4308 will reconnect the input equivalent bus capacitances on both sides of the bus. and output busses if a stop bit or bus idle condition is The Typical Performance Characteristics section shows detected, as specifi ed in the Start Up section. Alternatively, propagation delay as a function of temperature and voltage a rising edge on ENABLE forces the connection circuitry to for 2.7k pull-up resistors and 50pF equivalent capacitance reconnect the input and output busses and reset the 30ms on both sides of the part. Also, the Propagation Delay as timer if the bus remains in a stuck bus low condition. a function of Output Capacitance curve shows that larger 4308f 9
OPERATION
COUT = 50pF COUT = 50pF VPULLUP(OUT) = VCC = 3.3V VPULLUP(OUT) = VCC = 3.3V /DIV /DIV 1V 1V CIN = 150pF CIN = 150pF VPULLUP(IN) = 1.8V VPULLUP(IN) = 1.8V 200ns/DIV 200ns/DIV 4308 F02 4308 F03
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms Propagation Delays
output capacitances translate to longer delays. Users must quantify the difference in propagation times for a rising During a rising edge, the rise time on each side is infl u- edge versus a falling edge in their systems and adjust enced by rise time acceleration, bus pull-up resistor, and setup and hold times accordingly. the equivalent capacitance on the line. If the pull-up resis- tors are the same, a difference in rise time occurs which is
Bus Stuck Low Timeout
directly proportional to the difference in capacitance and SDAOUT and SCLOUT are each connected to an internal the presence of rise time acceleration between the two timer. When SDAOUT or SCLOUT is low, its respective sides. This effect is displayed in Figure 2 for VCC = 3.3V timer is started. Each timer is only reset when its pin goes and a 2.7k pull-up resistor on the input (VPULLUP(IN) = high. If the bus stuck low does not go high within 30ms 1.8V, CIN = 150pF) and output (VPULLUP(OUT) = 3.3V, COUT (typical), the connection circuitry is disabled, breaking = 50pF). Since the output pin has rise time acceleration the connection between the respective input and output and less capacitance than the input, it rises faster and pins. In addition, after at least 40μs, up to 16 clock pulses the effective propagation delay is negative. at 8.5kHz (typical) are generated on the SCLOUT pin by There is a fi nite propagation delay through the connec- the LTC4308 in an attempt to free the stuck low bus. The tion circuitry for falling waveforms. Figure 3 shows the clock pulses are halted if the bus recovers to a logic high falling edge waveforms for the same pull-up resistors and condition before the completion of the full 16 pulses. A equivalent capacitance conditions as used in Figure 2. stop bit is always generated on the SCLOUT and SDAOUT An external N-channel MOSFET device pulls down the pins to reset all devices on the bus. voltage on the side with 150pF capacitance; the LTC4308 If the stuck low SDAOUT or SCLOUT does not recover to pulls down the voltage on the opposite side with a delay a logic high condition after the automatic clocking and of 70ns. This delay is always positive and is a function of stop bit generation, the LTC4308 remains disconnected. supply voltage, temperature and the pull-up resistors and Should the bus free, the LTC4308 will reconnect the input equivalent bus capacitances on both sides of the bus. and output busses if a stop bit or bus idle condition is The Typical Performance Characteristics section shows detected, as specifi ed in the Start Up section. Alternatively, propagation delay as a function of temperature and voltage a rising edge on ENABLE forces the connection circuitry to for 2.7k pull-up resistors and 50pF equivalent capacitance reconnect the input and output busses and reset the 30ms on both sides of the part. Also, the Propagation Delay as timer if the bus remains in a stuck bus low condition. a function of Output Capacitance curve shows that larger 4308f 9