Datasheet LTC4307-1 (Analog Devices) - 8

LTC4307-1
OPERATION Start-Up Input to Output Offset Voltage
When the LTC4307-1 fi rst receives power on its VCC pin When a logic low voltage, VLOW1, is driven on any of the during power-up, it starts in an undervoltage lockout LTC4307-1’s data or clock pins, the LTC4307-1 regulates (UVLO) state, ignoring any activity on the SDA or SCL the voltage on the opposite data or clock pins to a slightly pins until VCC rises above 2V (typ). This is to ensure that higher voltage, typically 60mV above VLOW1. This offset is the LTC4307-1 does not try to function until it has enough practically independent of pull-up current (see the Typical voltage to do so. Performance curves). Once the LTC4307-1 comes out of UVLO, it monitors both
Propagation Delays
2-wire busses for either a stop bit or bus idle condition to indicate the completion of data transactions. When both During a rising edge, the rise time on each side is de- sides are idle or one side has a stop bit condition while the termined by the bus pull-up resistor and the equivalent other is idle, the input-to-output connection circuitry is acti- capacitance on the line. If the pull-up resistors are the vated, joining SDAIN to SDAOUT and SCLIN to SCLOUT. same, a difference in rise time occurs which is directly proportional to the difference in capacitance between
Connection Circuitry
the two sides. Users must account for differences in the Once the connection circuitry is activated, the functionality RC time constants between the two 2-wire busses and of the SDAIN and SDAOUT pins is identical. A low forced ensure that all system timing specifi cations are met on on either pin at any time results in both pin voltages being both busses. low. The LTC4307-1 is tolerant of I2C bus DC logic low There is a fi nite propagation delay through the connection voltages up to the 0.3VCC VIL I2C specifi cation. circuitry for falling waveforms. Figure 2 shows the falling When the LTC4307-1 senses a rising edge on the bus, edge waveforms for VCC = 5.5V, a 10k pull-up resistor on it deactivates its pull-down devices for bus voltages as each side, 150pF parasitic capacitance on the input bus and low as 0.48V. Care must be taken to ensure that devices 50pF on the output pins. An external N-channel MOSFET participating in clock stretching or arbitration force logic device pulls down the voltage on the side with 150pF low voltages below 0.48V at the LTC4307-1 inputs. capacitance; the LTC4307-1 pulls down the voltage on the opposite side with a delay of 80ns. This delay is always SDAIN and SDAOUT enter a logic high state only when positive and is a function of supply voltage, temperature all devices on both SDAIN and SDAOUT release high. and the pull-up resistors and equivalent bus capacitances The same is true for SCLIN and SCLOUT. This important on both sides of the bus. The Typical Performance Charac- feature ensures that clock stretching, clock synchroniza- teristics section shows propagation delay as a function of tion, arbitration and the acknowledge protocol always temperature and voltage for 10k pull-up resistors and 50pF work, regardless of how the devices in the system are equivalent capacitance on both sides of the part. Also, the tied to the LTC4307-1. tPHL vs COUT curve for VCC = 5.5V shows that increasing the Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the capacitances of the two 2-wire busses isolated from each other. Plac- ing an LTC4307-1 close to an HDMI port inside an HDMI INPUT SIDE OUTPUT SIDE 150pF 50pF transmitter or receiver allows the HDMI device to pass 1V/DIV 1V/DIV the capacitance compliance specifi cation. Because of this isolation, the waveforms on SDAIN and SCLIN look slightly 200ns/DIV 43071 F02 different than the corresponding waveforms on SDAOUT and SCLOUT as described here.
Figure 2. Input-Output Falling Edge Waveforms
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