Datasheet LTC4306 (Analog Devices) - 4

LTC4306
ELECTRICAL CHARACTERISTICS The
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denotes specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25
°
C. VCC = 3.3V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VALERT1-4(IN) ALERT1-ALERT4 Pin Input Falling ● 0.8 1.0 1.2 V Threshold Voltages VALERT1-4(HY) ALERT1-ALERT4 Pin Input Threshold 80 mV Hysteresis Voltages
I2C Interface
VADR(H) ADR0-2 Input High Voltage ● 0.75 • VCC 0.9 • VCC V VADR(L) ADR0-2 Input Low Voltage ● 0.1 • VCC 0.25 • VCC V IADR(IN, L) ADR0-2 Logic Low Input Current ADR0-2 = 0V, VCC = 5.5V ● –30 –60 –80 µA IADR(FLOAT) ADRO-2 Allowed Input Current VCC = 2.7V, 5.5V (Note 5) ● ±5 ±13 µA IADR(IN, H) ADR0-2 Logic High Input Current ADR0-2 = VCC = 5.5V ● 30 60 80 µA VSDAIN,SCLIN(TH) SDAIN, SCLIN Input Falling Threshold VCC = 5.5V ● 1.4 1.6 1.8 V Voltages VSDAIN,SCLIN(HY) SDAIN, SCLIN Hysteresis 30 mV ISDAIN,SCLIN(OH) SDAIN, SCLIN Input Current SCL, SDA = VCC ● 0 ±5 µA CIN SDA, SCL Input Capacitance (Note 2) 6 pF VSDAIN(OL) SDAIN Output Low Voltage ISDA = 4mA, VCC = 2.7V ● 0.2 0.4 V
I2C Interface Timing
fSCL Maximum SCL Clock Frequency (Note 2) 400 kHz tBUF Bus Free Time Between Stop/Start Condition (Note 2) 0.75 1.3 µs tHD,STA Hold Time After (Repeated) Start Condition (Note 2) 45 100 ns tSU,STA Repeated Start Condition Set-up Time (Note 2) –30 0 ns tSU,STO Stop Condition Set-up Time (Note 2) –30 0 ns tHD,DATI Data Hold Time Input (Note 2) –25 0 ns tHD,DATO Data Hold Time Output (Note 2) 300 600 900 ns tSU,DAT Data Set-up Time (Note 2) 50 100 ns tf SCL, SDA Fall Times (Note 2) 20 + 0.1 • 300 ns CBUS tSP Pulse Width of Spikes Suppressed by the (Note 2) 50 150 250 ns Input Filter
Note 1:
Absolute Maximum Ratings are those values beyond which the life to a voltage VLOW2 = VLOW + VOS, where VOS is a positive offset voltage. of a device may be impaired. VOS,UP-BUF is the offset voltage when the LTC4306 is driving the upstream
Note 2:
Guaranteed by design and not subject to test. pin (e.g., SDAIN) and VOS,DOWN-BUF is the offset voltage when the
Note 3:
The boosted pull-up currents are regulated to prevent excessively LTC4306 is driving the downstream pin (e.g., SDA1). See the Typical fast edges for light loads. See the Typical Performance Characteristics for Performance Characteristics for VOS,UP-BUF and VOS,DOWN-BUF as a rise time as a function of V function of VCC and bus pull-up current. CC and parasitic bus capacitance CBUS and for I
Note 5:
When floating, the ADR0-ADR2 pins can tolerate pin leakage BOOST as a function of VCC and temperature.
Note 4:
When a logic low voltage, V currents up to IADR(FLOAT) and still convert the address correctly. LOW, is forced on one side of the Upstream-Downstream Buffers, the voltage on the other side is regulated 4306f 4