Datasheet LTC4300A-1, LTC4300A-2 (Analog Devices) - 9

LTC4300A-1/LTC4300A-2
OPERATION
OUTPUT INPUT INPUT OUTPUT SIDE SIDE SIDE SIDE 50pF 150pF 150pF 50pF 4300a12 F01 4300a12 F02
Figure 1. Input–Output Connection tPLH Figure 2. Input–Output Connection tPHL
supply voltage, temperature and the pull-up resistors and using the rise-time accelerators, which are activated at a equivalent bus capacitances on both sides of the bus. The DC threshold of below 0.65V, the worst-case rise-time is: Typical Performance Characteristics section shows tPHL (2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the as a function of temperature and voltage for 10k pull-up 1μs rise-time requirement. resistors and 100pF equivalent capacitance on both sides of the part. By comparison with Figure 2, the V
READY Digital Output (LTC4300A-1)
CC = 3.3V curve shows that increasing the capacitance from 50pF This pin provides a digital flag which is low when either to 100pF results in a tPHL increase from 55ns to 75ns. ENABLE is low or the start-up sequence described earlier Larger output capacitances translate to longer delays (up in this section has not been completed. READY goes high to 150ns). Users must quantify the difference in propaga- when ENABLE is high and start-up is complete. The pin tion times for a rising edge versus a falling edge in their is driven by an open drain pull-down capable of sinking systems and adjust setup and hold times accordingly. 3mA while holding 0.4V on the pin. Connect a resistor of 10k to V
Rise-Time Accelerators
CC to provide the pull-up. This feature is available for the LTC4300A-1 only. Once connection has been established, rise-time accelera- tor circuits on all four SDA and SCL pins are activated.
ENABLE Low Current Disable (LTC4300A-1)
These allow the user to choose weaker DC pull-up cur- Grounding the ENABLE pin disconnects the backplane side rents on the bus, reducing power consumption while still from the card side, disables the rise-time accelerators, meeting system rise-time requirements. During positive drives READY low, disables the bus precharge circuitry bus transitions, the LTC4300A switches in 2mA (typical) and puts the part in a near-zero current state. When the of current to quickly slew the SDA and SCL lines once pin voltage is driven all the way to VCC, the part waits for their DC voltages exceed 0.6V. Using a general rule of data transactions on both the backplane and card sides to 20pF of capacitance for every device on the bus (10pF for be complete (as described in the Start-Up section) before the device and 10pF for interconnect), choose a pull-up reconnecting the two sides. This feature is available for current so that the bus will rise on its own at a rate of at the LTC4300A-1 only. least 1.25V/μs to guarantee activation of the accelerators. For example, assume an SMBus system with V
ACC Boost Current Enable (LTC4300A-2)
CC = 3V, a 10k pull-up resistor and equivalent bus capacitance of Users having lightly loaded systems may wish to disable 200pF. The rise-time of an SMBus system is calculated the rise-time accelerators. Driving this pin to ground turns from (VIL(MAX) – 0.15V) to (VIH(MIN) + 0.15V), or 0.65V off the rise-time accelerators on all four SDA and SCL to 2.25V. It takes an RC circuit 0.92 time constants to pins. Driving this pin to the VCC2 voltage enables normal traverse this voltage for a 3V supply; in this case, 0.92 operation of the rise-time accelerators, as described in • (10k • 200pF) = 1.84μs. Thus, the system exceeds the the Rise-Time Accelerators section above. This feature is maximum allowed rise-time of 1μs by 84%. However, available for the LTC4300A-2 only. 4300a12fa 9